{"id":22188780,"url":"https://github.com/aliiiw/computer-architecture-lab","last_synced_at":"2026-02-21T22:05:39.178Z","repository":{"id":234049165,"uuid":"561665455","full_name":"Aliiiw/Computer-Architecture-Lab","owner":"Aliiiw","description":"Implement Mips cpu with Verilog","archived":false,"fork":false,"pushed_at":"2023-01-22T10:34:48.000Z","size":892,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-10-26T05:40:30.814Z","etag":null,"topics":["forwarding","mips","pipeline","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Aliiiw.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-11-04T07:55:15.000Z","updated_at":"2023-03-08T14:44:38.000Z","dependencies_parsed_at":null,"dependency_job_id":"d0d71c38-30ee-40df-acf4-ff8c3fee5e84","html_url":"https://github.com/Aliiiw/Computer-Architecture-Lab","commit_stats":null,"previous_names":["aliiiw/computer-architecture-lab"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/Aliiiw/Computer-Architecture-Lab","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Aliiiw%2FComputer-Architecture-Lab","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Aliiiw%2FComputer-Architecture-Lab/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Aliiiw%2FComputer-Architecture-Lab/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Aliiiw%2FComputer-Architecture-Lab/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Aliiiw","download_url":"https://codeload.github.com/Aliiiw/Computer-Architecture-Lab/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Aliiiw%2FComputer-Architecture-Lab/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29694840,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-21T18:18:25.093Z","status":"ssl_error","status_checked_at":"2026-02-21T18:18:22.435Z","response_time":107,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["forwarding","mips","pipeline","verilog"],"created_at":"2024-12-02T11:12:29.602Z","updated_at":"2026-02-21T22:05:39.161Z","avatar_url":"https://github.com/Aliiiw.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Computer-Architecture-Lab\nImplement Mips cpu with Verilog\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faliiiw%2Fcomputer-architecture-lab","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Faliiiw%2Fcomputer-architecture-lab","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faliiiw%2Fcomputer-architecture-lab/lists"}