{"id":26365043,"url":"https://github.com/alirezakay/risc-cpu","last_synced_at":"2026-01-03T11:51:35.940Z","repository":{"id":53853344,"uuid":"143284283","full_name":"alirezakay/RISC-CPU","owner":"alirezakay","description":"A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )","archived":false,"fork":false,"pushed_at":"2021-06-19T15:03:03.000Z","size":2639,"stargazers_count":22,"open_issues_count":0,"forks_count":3,"subscribers_count":2,"default_branch":"master","last_synced_at":"2023-03-21T11:08:48.868Z","etag":null,"topics":["cpu","cpu-architecture","cpu-model","instruction-set-architecture","isa","mips-processor","multi-cycle","processor-architecture","processor-design","risc-processor","vhdl","vhdl-code","vhdl-modules"],"latest_commit_sha":null,"homepage":"https://alirezakay.github.io/showcase/term4","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/alirezakay.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2018-08-02T11:13:16.000Z","updated_at":"2023-02-27T02:19:03.000Z","dependencies_parsed_at":"2022-08-23T11:10:59.483Z","dependency_job_id":null,"html_url":"https://github.com/alirezakay/RISC-CPU","commit_stats":null,"previous_names":[],"tags_count":null,"template":null,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alirezakay%2FRISC-CPU","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alirezakay%2FRISC-CPU/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alirezakay%2FRISC-CPU/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alirezakay%2FRISC-CPU/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/alirezakay","download_url":"https://codeload.github.com/alirezakay/RISC-CPU/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243919579,"owners_count":20368912,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","cpu-architecture","cpu-model","instruction-set-architecture","isa","mips-processor","multi-cycle","processor-architecture","processor-design","risc-processor","vhdl","vhdl-code","vhdl-modules"],"created_at":"2025-03-16T19:29:33.996Z","updated_at":"2026-01-03T11:51:35.916Z","avatar_url":"https://github.com/alirezakay.png","language":"VHDL","readme":"# RISC-CPU\n\u003e A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )\n\n## Documentation\nThis project is implemented in `VHDL` language with `ISE` simulator software with **a particular specifications**.\n\nRelevant course for this project could be `computer architecture`.\n\nThese codes here in github, are just the vhdl and wave files.\n\nIf you wanna get the ***complete project codes, built with `ISE`*** go [here](https://alirezakay.github.io/showcase/y2/risc-cpu-simulation), find the project title and **download** the full one.\n\nhere is a fairly complete documentaion written in **Persian** and also **English** languages: [document](./MyCPU.pdf)\n\n\u003chr /\u003e\n\n![image 1 - cpu](https://alirezakay.github.io/showcase/y2/img/CPU2.png)\n\n![image 2 - cpu](https://alirezakay.github.io/showcase/y2/img/CPU3.png)\n\n\u003chr /\u003e\n\n## Authors\n\n[Alireza Kavian](https://alireza-kavian.github.io)\n\n## License\n\nThis project is licensed under the MIT License - see the [LICENSE](./LICENSE) file for details\n\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falirezakay%2Frisc-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Falirezakay%2Frisc-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falirezakay%2Frisc-cpu/lists"}