{"id":21297970,"url":"https://github.com/amamory/data2mem_modify_bitstream","last_synced_at":"2026-03-19T19:45:57.924Z","repository":{"id":168583304,"uuid":"314672368","full_name":"amamory/data2mem_modify_bitstream","owner":"amamory","description":"testing data2mem to add the content of an .elf into the bitstream","archived":false,"fork":false,"pushed_at":"2020-11-21T22:47:19.000Z","size":99,"stargazers_count":2,"open_issues_count":1,"forks_count":1,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-01-22T07:33:23.350Z","etag":null,"topics":["bitstream","extract-bmm","fpga","vivado"],"latest_commit_sha":null,"homepage":"","language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/amamory.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-11-20T21:21:36.000Z","updated_at":"2022-06-09T13:11:25.000Z","dependencies_parsed_at":null,"dependency_job_id":"7b5bc716-b4c7-4f23-8c9a-7caafd8722da","html_url":"https://github.com/amamory/data2mem_modify_bitstream","commit_stats":null,"previous_names":["amamory/data2mem_modify_bitstream"],"tags_count":0,"template":false,"template_full_name":"amamory/vivado-base-project","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/amamory%2Fdata2mem_modify_bitstream","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/amamory%2Fdata2mem_modify_bitstream/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/amamory%2Fdata2mem_modify_bitstream/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/amamory%2Fdata2mem_modify_bitstream/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/amamory","download_url":"https://codeload.github.com/amamory/data2mem_modify_bitstream/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243769946,"owners_count":20345215,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["bitstream","extract-bmm","fpga","vivado"],"created_at":"2024-11-21T14:42:54.824Z","updated_at":"2026-01-03T02:06:08.054Z","avatar_url":"https://github.com/amamory.png","language":"Tcl","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Vivado Bitstream Modify\n\nThis repo has a design to test bitstream modification to insert data from an .elf file into BRAMs.\n\n# The Example Block Design\n\nThis design uses the Zynq connected to two independent memory banks, called\n*blk_mem_gen_0* and *blk_mem_gen_1*, both configured with single port, \n32bits data width, and 8192 addr depth. \n\n![Block](block.png)\n\nWhen executing the TCL command in the Vivado terminal\n\n```\n$ get_cells -hier -filter {PRIMITIVE_TYPE =~ BMEM.*.*}\n```\n\nThe output is \n\n   - design_1_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.SP.SIMPLE_PRIM36.SP_NO_ECC_ATTR.ram\n   - design_1_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.SP.SIMPLE_PRIM36.SP_NO_ECC_ATTR.ram\n   - design_1_i/blk_mem_gen_1/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.SP.SIMPLE_PRIM36.SP_NO_ECC_ATTR.ram\n   - design_1_i/blk_mem_gen_1/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.SP.SIMPLE_PRIM36.SP_NO_ECC_ATTR.ram\n\nrepresenting the BRAMs in the design. The 1st two cell belongs to the memory block blk_mem_gen_0 while the last two are from block blk_mem_gen_1.\n\n\n# The BMM Extraction\n\nThe extract_bmm.tcl opens the synthesized design, finds the existing BRAMs,\nand map them into the memory blocks *blk_mem_gen_0* and *blk_mem_gen_1*.\n\nThe resulting BMM file is like this\n\n```\nADDRESS_SPACE memory_0 COMBINED [0x00000000:0x000001FFF]\nADDRESS_RANGE RAMB32\n   BUS_BLOCK\n      bit_modif_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.SP.SIMPLE_PRIM36.SP_NO_ECC_ATTR.ram [0] [15:0] LOC=X3Y20;\n      bit_modif_i/blk_mem_gen_0/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.SP.SIMPLE_PRIM36.SP_NO_ECC_ATTR.ram [1] [31:16] LOC=X3Y19;\n   END_BUS_BLOCK;\nEND_ADDRESS_RANGE;\nEND_ADDRESS_SPACE;\n\nADDRESS_SPACE memory_1 COMBINED [0x00000000:0x000001FFF]\nADDRESS_RANGE RAMB32\n   BUS_BLOCK\n      bit_modif_i/blk_mem_gen_1/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.SP.SIMPLE_PRIM36.SP_NO_ECC_ATTR.ram [0] [15:0] LOC=X3Y22;\n      bit_modif_i/blk_mem_gen_1/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.SP.SIMPLE_PRIM36.SP_NO_ECC_ATTR.ram [1] [31:16] LOC=X3Y21;\n   END_BUS_BLOCK;\nEND_ADDRESS_RANGE;\n```\n\nBy the end of the [extract_bmm.tcl](./extract_bmm.tcl) TCL script, *data2mem* is executed in the Linux terminal to insert the elf file into the bitstream *new.bit*.\n\n```\n$ data2mem -bm mem_dump.bmm -bd ./src/processor-based/image.elf -bt ./vivado/bit_modif/bit_modif.runs/impl_1/bit_modif_wrapper.bit -o b new.bit\n```\n\nTo check whether the new bitstream is updated, it is possible to dump the BRAM's content with\nthe following command in the Linux terminal:\n\n```\n$ data2mem -bm mem_dump.bmm -bt new.bit -d \u003e dump.txt\n```\n\nThen open the dump.txt and search for *bit_modif_i* to find the written BRAMs.\n\n\n# How to run it\n\nThese scripts are assuming Linux operation system (Ubuntu 18.04) and Vivado 2018.2.\n\nFollow these instructions to recreate the Vivado and SDK projects:\n - Open the **build.sh** script and edit the first lines to setup these environment variables:\n    - **VIVADO**: path to the Vivado install dir;\n    - **VIVADO_DESIGN_NAME**: mandatory name of the design;\n    - **XIL_APP_NAME**: used only in projects with software;\n    - **VIVADO_TOP_NAME**: set the top name (optional).  \n - run *build.sh*\n\nThese scripts will recreate the entire Vivado project, compile the design, generate the bitstream, update the bitstream with the elf file, export the hardware to SDK, create the SDK projects, import the source files, build all projects, and finally download both the bitstream and the elf application. Hopefully, all these steps will be executed automatically.\n\n# How to update the scripts\n\nThese scripts come from a template repository and they get updated and improved over time. If you wish to get the latest script version, then follow these steps:\n\n```\ngit remote add template https://github.com/amamory/vivado-base-project.git\ngit fetch --all\ngit merge --no-commit --no-ff template/master --allow-unrelated-histories\n```\n\nSolve any conflict manually and then commit.\n\n# Future work\n\n - use also [updatemem](https://www.xilinx.com/support/answers/63041.html)\n \n# How to Use Vivado\n\n[Vipin Kizheppatt](https://www.youtube.com/watch?v=ahws--oNpBc\u0026list=PLXHMvqUANAFOviU0J8HSp0E91lLJInzX1) provides a great set of more than 70 extremely didatic videos. As a personal experience, I would strongly suggest that as a starting point.\n\n# Credits\n\nThe scripts are based on the excellent scripts from [fpgadesigner](https://github.com/fpgadeveloper/zedboard-axi-dma) plus few increments from my own such as project generalization, support to SDK project creation and compilation and other minor improvements. \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Famamory%2Fdata2mem_modify_bitstream","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Famamory%2Fdata2mem_modify_bitstream","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Famamory%2Fdata2mem_modify_bitstream/lists"}