{"id":28520281,"url":"https://github.com/anirudh-bijay/iitk-mini-mips","last_synced_at":"2026-05-16T13:03:23.898Z","repository":{"id":297102040,"uuid":"958983193","full_name":"anirudh-bijay/IITK-Mini-MIPS","owner":"anirudh-bijay","description":"Repository for project work for the course CS220: Computer Organisation.","archived":false,"fork":false,"pushed_at":"2025-05-05T21:09:50.000Z","size":530,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-06-04T05:34:23.071Z","etag":null,"topics":["assembler","python","single-cycle-mips-processor","university-project","verilog","vivado"],"latest_commit_sha":null,"homepage":"","language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/anirudh-bijay.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2025-04-02T04:41:42.000Z","updated_at":"2025-06-03T14:07:51.000Z","dependencies_parsed_at":"2025-06-04T05:35:26.318Z","dependency_job_id":"2f60a1dc-7304-4cdb-bdd5-176a5c9a7c2c","html_url":"https://github.com/anirudh-bijay/IITK-Mini-MIPS","commit_stats":null,"previous_names":["anirudh-bijay/iitk-mini-mips"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/anirudh-bijay/IITK-Mini-MIPS","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/anirudh-bijay%2FIITK-Mini-MIPS","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/anirudh-bijay%2FIITK-Mini-MIPS/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/anirudh-bijay%2FIITK-Mini-MIPS/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/anirudh-bijay%2FIITK-Mini-MIPS/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/anirudh-bijay","download_url":"https://codeload.github.com/anirudh-bijay/IITK-Mini-MIPS/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/anirudh-bijay%2FIITK-Mini-MIPS/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":266413524,"owners_count":23924745,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-07-22T02:00:09.085Z","response_time":66,"last_error":null,"robots_txt_status":null,"robots_txt_updated_at":null,"robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembler","python","single-cycle-mips-processor","university-project","verilog","vivado"],"created_at":"2025-06-09T07:01:40.943Z","updated_at":"2026-05-16T13:03:23.886Z","avatar_url":"https://github.com/anirudh-bijay.png","language":"Tcl","funding_links":[],"categories":[],"sub_categories":[],"readme":"# IITK Mini-MIPS\n\nIITK Mini-MIPS is an extended and slightly modified version of the MIPS instruction set\narchitecture. IITK Mini-MIPS assumes a Harvard architecture with the word size and\ninstruction width both fixed at 32 bits. The architecture mandates 32 general-purpose\nregisters and a floating point coprocessor with 32 floating point registers and support\nfor addition, subtraction, and comparisons.\n\nHere, we design the microarchitecture of a single-cycle processor implementing the ISA\nin Verilog. The AMD Vivado™ Design Suite was used to implement the design and test it\non a PYNQ-Z2 FPGA development board.\n\nThis project is undertaken in partial fulfilment of the requirements of the course\n[CS220: Computer Organisation](https://www.cse.iitk.ac.in/pages/CS220.html) offered at\n[IIT Kanpur](https://iitk.ac.in) in Winter 2025 instructed by\n[Prof. Debapriya Basu Roy](https://www.cse.iitk.ac.in/users/dbroy).\n\n## Building the Project\n\nYou will need the [AMD Vivado™ Design Suite](https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html)\nto build the project.\n\nTo build, simply add all files under the [`src`](src) and [`ip`](ip)\ndirectories into a new Vivado project; include the test bench under\n[`src/test_benches`](src/test_benches) as a simulation source, and\nall other files as design sources. Alternatively, you may run the Tcl\nscript [`build.tcl`](build.tcl) from the Vivado Tcl Shell.\n\n\u003e If, on adding the files, the IPs show up as 'locked', right-click on each\n  locked IP in the *Sources* tab and select 'Upgrade IP'.\n\n## Usage Instructions\n\nTo run a program:\n\n1. Use the [assembler](assembler.py) to generate a COE file\n    using the following command:\n\n    ```powershell\n    python assembler.py INPUT_FILE -o OUTPUT_FILE -coe\n    ```\n\n    Note that you need Python 3.11 or above installed to run the assembler.\n\n    The output file must be placed in the folder\n    [`ip/simple_dual_port_distributed_ram_0`](ip/simple_dual_port_distributed_ram_0)\n    and should have a `.coe` file extension. For help on the assembler,\n    invoke it with the `--help` (`-h`) flag.\n\n    ```powershell\n    python assembler.py -h\n    ```\n\n    #### Example\n\n    [`factorial.s`](factorial.s) contains an example assembly program that\n    computes the factorial of a whole number. It demonstrates jumps using\n    absolute addresses, branches using PC-relative offsets, and read-write\n    operations on memory-mapped I/O using polling.\n\n    ```powershell\n    python assembler.py factorial.s -o ip/simple_dual_port_distributed_ram_0/factorial.coe -coe\n    ```\n    \n    \u003e The `.coe` file places the instructions in your program in the\n    instruction memory sequentially starting from address `0x0`. Jump\n    addresses in the assembly program should take this into account.\n\n2. In Vivado, right-click on `simple_dual_port_distributed_ram_0` in the\n    *Sources* tab and select 'Re-customize IP'.\n\n3. In the window that opens, go to the *RST \u0026 Initialization* tab and select\n    the previously generated `.coe` file as the coefficients file. Click 'OK'\n    to save your changes and regenerate the IP output products.\n\n4. For simulation as well as for running on an FPGA, the processor's `clk`\n    input must be connected to a clock source and its `rst` signal must be\n    asserted at the start. Thereafter, `rst` should be deasserted; execution\n    then starts from the first instruction in your program, loaded at address\n    `0x0`.\n\n## Results\n\nThe design was implemented on a PYNQ-Z2 FPGA development board interfaced with\nthe Zynq-7000 Processing System at a clock frequency of 40.000 MHz. The\nimplemented design had an LUT count of 1797 and utilised 13 DSP slices.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fanirudh-bijay%2Fiitk-mini-mips","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fanirudh-bijay%2Fiitk-mini-mips","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fanirudh-bijay%2Fiitk-mini-mips/lists"}