{"id":13648983,"url":"https://github.com/antmicro/usb-test-suite-build","last_synced_at":"2025-04-22T11:33:29.350Z","repository":{"id":48313315,"uuid":"208862639","full_name":"antmicro/usb-test-suite-build","owner":"antmicro","description":"Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores","archived":false,"fork":false,"pushed_at":"2023-08-07T13:43:53.000Z","size":230,"stargazers_count":50,"open_issues_count":6,"forks_count":10,"subscribers_count":13,"default_branch":"master","last_synced_at":"2024-11-09T23:36:27.543Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Shell","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/antmicro.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-09-16T17:53:06.000Z","updated_at":"2024-10-30T02:53:27.000Z","dependencies_parsed_at":"2024-11-09T23:31:08.469Z","dependency_job_id":"e5d34d4a-7fb4-4604-bc89-b1fb258ea2f0","html_url":"https://github.com/antmicro/usb-test-suite-build","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/antmicro%2Fusb-test-suite-build","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/antmicro%2Fusb-test-suite-build/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/antmicro%2Fusb-test-suite-build/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/antmicro%2Fusb-test-suite-build/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/antmicro","download_url":"https://codeload.github.com/antmicro/usb-test-suite-build/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250232617,"owners_count":21396669,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:41.259Z","updated_at":"2025-04-22T11:33:28.984Z","avatar_url":"https://github.com/antmicro.png","language":"Shell","funding_links":[],"categories":["Shell"],"sub_categories":[],"readme":"# USB test suite\n\nCopyright (c) 2019-2021 [Antmicro](https://www.antmicro.com)\n\nThis is a [Cocotb](https://github.com/cocotb/cocotb) based USB 1.1 test suite (to be extended to cover higher versions of the standard) for FPGA IP, with testbenches for a variety of open source USB cores. Cocotb enables testing IPs with Python, which makes for a very robust and developer-friendly workflow.\n\nThis repository is a top level repo, with libraries used by the project and specific testbenches and cores as submodules.\n\nDocumentation for this project is hosted at [Read the Docs](https://usb-test-suite.readthedocs.io/en/latest/index.html).\n\n## Setup\n\nIt is recommended that you use a virtualenv or similar tool.\nThis will be taken care of by the `setup.sh` script.\n\n### Prerequisites\n\n* python3\n* pip\n* iverilog\n\n### Steps\n\n```\n# Install dependencies\nsudo apt install python3 python3-pip iverilog\n# Clone the repository.\ngit clone https://github.com/antmicro/usb-test-suite-build.git\ncd usb-test-suite-build\n# Run script to setup environment\n./setup.sh\n```\n\n## Usage\n\nUse the Makefile in **usb-test-suite-testbenches** folder to choose the IP core and test module.\nCurrently we support testing:\n\n* [ValentyUSB](https://github.com/im-tomu/valentyusb)\n* [Foboot](https://github.com/im-tomu/foboot)\n* [asics-ws usb1_device](https://github.com/www-asics-ws/usb1_device)\n* [tnt's USB IP core](https://github.com/smunaut/ice40-playground/tree/master/cores/usb)\n* [TinyFPGA-Bootloader](https://github.com/tinyfpga/TinyFPGA-Bootloader)\n\nExecute tests by calling:\n\n```\n# Make sure you are in the virtualenv\n. env/bin/activate\ncd usb-test-suite-testbenches\n# Execute tests with default values\nmake sim\n```\n\nMake sure to run `make clean` when switching targets. See the README in **usb-test-suite-testbenches** for details.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fantmicro%2Fusb-test-suite-build","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fantmicro%2Fusb-test-suite-build","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fantmicro%2Fusb-test-suite-build/lists"}