{"id":13537390,"url":"https://github.com/antonblanchard/vlsiffra","last_synced_at":"2025-10-03T19:53:44.483Z","repository":{"id":49387513,"uuid":"497489874","full_name":"antonblanchard/vlsiffra","owner":"antonblanchard","description":"Create fast and efficient standard cell based adders, multipliers and multiply-adders.","archived":false,"fork":false,"pushed_at":"2023-09-20T20:59:45.000Z","size":3169,"stargazers_count":112,"open_issues_count":17,"forks_count":9,"subscribers_count":7,"default_branch":"main","last_synced_at":"2025-04-15T16:52:50.700Z","etag":null,"topics":["adder","amaranth-hdl","booth","dadda","multiplier","physical-design","verilog","vlsi"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/antonblanchard.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2022-05-29T04:31:53.000Z","updated_at":"2025-04-07T23:56:19.000Z","dependencies_parsed_at":"2024-04-23T19:06:04.639Z","dependency_job_id":"f7fbca54-2064-47fc-8f21-c74788fcdd13","html_url":"https://github.com/antonblanchard/vlsiffra","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/antonblanchard/vlsiffra","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/antonblanchard%2Fvlsiffra","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/antonblanchard%2Fvlsiffra/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/antonblanchard%2Fvlsiffra/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/antonblanchard%2Fvlsiffra/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/antonblanchard","download_url":"https://codeload.github.com/antonblanchard/vlsiffra/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/antonblanchard%2Fvlsiffra/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":278219766,"owners_count":25950350,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-10-03T02:00:06.070Z","response_time":53,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["adder","amaranth-hdl","booth","dadda","multiplier","physical-design","verilog","vlsi"],"created_at":"2024-08-01T09:00:58.485Z","updated_at":"2025-10-03T19:53:44.461Z","avatar_url":"https://github.com/antonblanchard.png","language":"Python","funding_links":[],"categories":["Libraries"],"sub_categories":[],"readme":"![vlsiffra logo](/media/vlsiffra.png)\n\nCreate fast and efficient standard cell based adders, multipliers and\nmultiply-adders.\n\n[![CI status](https://github.com/antonblanchard/vlsiffra/actions/workflows/test.yml/badge.svg)](https://github.com/antonblanchard/vlsiffra/actions/workflows/test.yml)\n[![GitHub tag](https://img.shields.io/github/v/tag/antonblanchard/vlsiffra)](https://github.com/antonblanchard/vlsiffra/tags/)\n[![License](https://img.shields.io/github/license/antonblanchard/vlsiffra)](https://opensource.org/licenses/Apache-2.0)\n[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat-square)](http://makeapullrequest.com)\n\n# Features\n\n## Fast\nA 2 cycle 64 bit multiply-adder (`64bit * 64bit + 128bit -\u003e 128bit`) built with\nthe [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD) RTL to GDSII\nflow and the [ASAP7](https://github.com/The-OpenROAD-Project/asap7) 7nm\nacademic PDK makes timing at 1.85 GHz [^1]. It takes up 3600um of area:\n\n![2 cycle 64 bit ASAP7 multiplier](media/asap7-gds.png)\n\nA 4 cycle 32 bit multiplier (`32bit * 32bit -\u003e 64bit`), also using OpenROAD and\nASAP7 makes timing at 2.7 GHz [^1]. Both cases are likely to improve as OpenROAD\nimproves (including better timing aware global placement and global routing,\nimprovements to the resizer, improvements to clock tree synthesis and the use of\nLVT cells).\n\nvlsiffra achieves this by using many well established techniques\nincluding\n[Booth encoding](https://en.wikipedia.org/wiki/Booth%27s_multiplication_algorithm),\n[Dadda reduction](https://en.wikipedia.org/wiki/Dadda_multiplier) and a choice\nof fast adders like\n[Kogge-Stone](https://en.wikipedia.org/wiki/Kogge%E2%80%93Stone_adder).\n\nFor more details about these algorithms, check out this\n[Twitter thread](https://twitter.com/antonblanchard/status/1540286905379524611)\nwhich details the implementation of the multiplier in the\n[Bluegene Q](https://en.wikipedia.org/wiki/IBM_Blue_Gene) supercomputer.\n\n## Configurable\n\nvlsiffra is written in the\n[Amaranth](https://github.com/amaranth-lang/amaranth) HDL language which allows\nit to be very configurable, including:\n\n- Configurable number of bits\n\n  Any power of two likely works, although Amaranth does start to slow down when\n  building 64 bit multipliers due to a polynomial time complexity issue when\n  adding signals. An\n  [issue](https://github.com/amaranth-lang/amaranth/issues/711) has been opened\n  to track this and once fixed larger multipliers should be possible.\n\n- Choice of algorithms\n\n  Various addition algorithms are supported:\n  - [Brent-Kung](https://en.wikipedia.org/wiki/Brent%E2%80%93Kung_adder)\n    (less area, lower performance)\n  - [Kogge-Stone](https://en.wikipedia.org/wiki/Kogge%E2%80%93Stone_adder)\n    (more area, higher performance)\n  - Han-Carlson (a balance of area and performance)\n  - [Ripple](https://en.wikipedia.org/wiki/Adder_(electronics)#Ripple-carry_adder)\n    (lowest area, lowest performance)\n\n- Configurable number of stages\n\n  Configurable number of stages, from purely combinational, to 4 register\n  stages. All configurations are fully pipelined. Trade latency for frequency.\n\n## Formally verified\n\n[Yosys](https://github.com/YosysHQ/yosys) is used to formally verify the\nstandard cell implementation matches gold behavioural models. Amaranth unit\ntests and [Verilator](https://www.veripool.org/verilator/) based tests are also\nused to further verify the design.\n\n## Support for many technologies.\n\nvlsiffra currently supports the\n[SkyWater sky130hd](https://github.com/google/skywater-pdk),\n[GlobalFoundries GF180MCU](https://github.com/google/gf180mcu-pdk) and\n[ASAP7](https://github.com/The-OpenROAD-Project/asap7) PDKs and standard cell\nlibraries.\n\n## Easy to add support for new technologies\nvlsiffra only requires a few standard cells (full and half adders,\n2 input xor, 2 input and, inverter as well as a couple of more complicated\ncells (ao21, ao22, ao33)\n\n# Installation\n\nvlsiffra is a python package, so this will install it and any\ndependencies:\n\n```\npip3 install git+https://github.com/antonblanchard/vlsiffra\n```\n\nAnother option is to install it from a checked out source tree:\n```\npip3 install .\n```\n\nAmaranth requires Yosys. If you don't have a version installed, you can use the\namaranth-yosys package:\n\n```\npip3 install amaranth-yosys\n```\n\n# Example usage\n\nCreate a GF180MCU 64 bit Kogge-Stone adder:\n\n```\nvlsi-adder --bits=64 --algorithm=koggestone --tech=gf180mcu --output=adder.v\n```\n\nCreate an ASAP7 32 bit multiplier, using a Brent-Kung adder:\n\n```\nvlsi-multiplier --bits=32 --algorithm=brentkung --tech=asap7 --output=multiplier.v\n```\n\nCreate a sky130hd 2 cycle 64 bit multiply-adder, which was taped out in the\nOpenPOWER [Microwatt](https://github.com/antonblanchard/microwatt) core for the\nGoogle/Efabless/SkyWater MPW7 shuttle (one for the fixed point multiplier and\nanother for the floating point multiplier):\n\n```\nvlsi-multiplier --bits=64 --multiply-add --algorithm=hancarlson --tech=sky130hd --register-post-ppg --output=multiply_adder_pipelined.v\n```\n\nThe two multipliers on the Microwatt MPW7 tape out can be seen on the left side\nof the die:\n\n![Microwatt MPW7 Multipliers](media/microwatt-mpw7-multipliers.png)\n\n# Testing\nLocal testing requires an installation of both yosys and verilator. Run\n`make check`.  Submitting a pull request will kick off the same set of tests.\n\n# Adding a new technology\n\nUsing ASAP7 as an example:\n\n- A [technology file](vlsiffra/tech/asap7.py) that contains code to\n  instantiate the standard cells required. Use one of the existing ones as a\n  starting point.\n\n  When creating instances, Amaranth uses the i_* prefix for inputs and the o_*\n  prefix for outputs, ie i_VDD means the instance has an input called VDD. As\n  an example, this instantiates the XOR2x1_ASAP7_75t_R xor cell that has A and\n  B inputs and a Y output.\n\n  Also note that ASAP7 inverts the outputs of the full and half adders, so you\n  will see inverters in this file to undo this. Remove them if your technology\n  has non inverting outputs.\n\n  eg Adding the xor definition:\n\n```\n      def _generate_xor(self, a, b, o):\n        xorgate = self._PoweredInstance(\n            \"XOR2x1_ASAP7_75t_R\",\n            i_A=a,\n            i_B=b,\n            o_Y=o\n        )\n\n        self.m.submodules += xorgate\n```\n\n- Modify [get_tech()](vlsiffra/tech/Tech.py) to hook the new tech up.\n\n- [Verilog behavioural models](verilog/asap7.v) for the standard cells, used\n  for verification.\n\n- Finally add the new technology to the CI [here](ci/formal.sh) and\n  [here](ci/verilator.sh).\n\n# Issues\n\n- No support for signed multipliers. Planning to add this.\n\n- No support for carry in or carry out of adders. Planning to add this.\n\n- No support for clock gating yet.\n\n- Formal verification of multipliers is slow, and gets unbearably slow as\n  the multiplier reaches 64 bits. As a result, we formally verify smaller\n  configurations only. We should check if we there are faster equivalence\n  checking methods in Yosys. Another idea might be to verify each output\n  bit in a different Yosys process, parallelising things.\n\n- Adding more optional register stages. Splitting Dadda reduction into two\n  cycles and perhaps final addition into two cycles would improve the\n  multiplier frequency.\n\n- We use OpenROAD for cell placement. We might be able to improve the area of\n  the design by doing manual placement, but it's not clear the effort is worth\n  it. We currently use Yosys to instantiate FFs, so we'd need to do this before\n  attempting manual placement.\n\n- Support for 4:2 compressors (basically 2 full adders). This is what\n  Bluegene Q uses and might help to improve area and frequency a bit. We'd\n  need to create a 4:2 compressor cell since none of the standard cell\n\n# Why vlsiffra?\nMy last attempt to name an Open Source project resulted in the impossible to\nGoogle for \"Microwatt\" OpenPOWER VHDL core. vlsiffra is a portmanteau of\nVLSI and siffra, the Swedish word for number. Thanks to @ruscur for the\nidea. Hello to all our Swedish readers.\n\n[^1]: ASAP7 RVT cells, STA at best corner, 50 ps reserved in the first and\nsecond cycles for input and output logic/routing outside the macro.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fantonblanchard%2Fvlsiffra","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fantonblanchard%2Fvlsiffra","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fantonblanchard%2Fvlsiffra/lists"}