{"id":19526156,"url":"https://github.com/antoninpvr/avr8bit-emu","last_synced_at":"2026-06-23T22:02:19.312Z","repository":{"id":255981101,"uuid":"854032699","full_name":"AntoninPvr/avr8bit-emu","owner":"AntoninPvr","description":"Simple 8bit emulator for AVR. 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Not all instructions are implemented yet. There are still large amounts of potentials flaws and bugs.\n\n## Implemented\n\nCore:\n\n- 32 8bit General purpose register\n- SREG flags register\n- 16bit SP stack pointer\n- 16bit PC program counter\n\n- SRAM memory\n\n## Arithmetic and logic instructions\n\n| mnemonic | description | status |\n| --- | --- | --- |\n| `ADC` | Add with carry | ❌ |\n| `ADD` | Add without carry | ❌ |\n| `ADIW` | Add immediate to word | ❌ |\n| `SUB` | Subtract without carry | ❌ |\n| `SUBI` | Subtract immediate | ❌ |\n| `SBC` | Subtract with carry | ❌ |\n| `SBCI` | Subtract immediate with carry | ❌ |\n| `SBIW` | Subtract immediate from word | ❌ |\n| `AND` | Logical AND | ❌ |\n| `ANDI` | Logical AND with immediate | ❌ |\n| `OR` | Logical OR | ❌ |\n| `ORI` | Logical OR with immediate | ❌ |\n| `EOR` | Logical Exclusive OR | ❌ |\n| `COM` | One's complement | ❌ |\n| `NEG` | Two's complement | ❌ |\n| `SBR` | Set bits in register | ❌ |\n| `CBR` | Clear bits in register | ❌ |\n| `INC` | Increment | ❌ |\n| `DEC` | Decrement | ❌ |\n| `TST` | Test for zero or minus | ❌ |\n| `CLR` | Clear register | ❌ |\n| `SER` | Set all bits in register | ❌ |\n| `MUL` | Multiply unsigned | ❌ |\n| `MULS` | Multiply signed | ❌ |\n| `MULSU` | Multiply signed with unsigned | ❌ |\n| `FMUL` | Fractional multiply unsigned | ❌ |\n| `FMULS` | Fractional multiply signed | ❌ |\n| `FMULSU` | Fractional multiply signed with unsigned | ❌ |\n| `DES` | Data encryption | ❌ |\n\n## Branch instruction\n\n| mnemonic | description | status |\n| --- | --- | --- |\n| `RJMP` | Relative jump | ❌ |\n| `IJMP` | Indirect jump | ❌ |\n| `EIJMP` | Extended indirect jump | ❌ |\n| `JMP` | Jump | ❌ |\n| `RCALL` | Relative call subroutine | ❌ |\n| `ICALL` | Indirect call subroutine | ❌ |\n| `EICALL` | Extended indirect call subroutine | ❌ |\n| `CALL` | Call subroutine | ❌ |\n| `RET` | Return from subroutine | ❌ |\n| `RETI` | Return from interrupt | ❌ |\n| `CPSE` | Compare, skip if equal | ❌ |\n| `CP` | Compare | ❌ |\n| `CPC` | Compare with carry | ❌ |\n| `CPI` | Compare with immediate | ❌ |\n| `SBRC` | Skip if bit in register cleared | ❌ |\n| `SBRS` | Skip if bit in register set | ❌ |\n| `SBIC` | Skip if bit in I/O register cleared | ❌ |\n| `SBIS` | Skip if bit in I/O register set | ❌ |\n| `BRBS` | Branch if status flag set | ❌ |\n| `BRBC` | Branch if status flag cleared | ❌ |\n| `BREQ` | Branch if equal | ❌ |\n| `BRNE` | Branch if not equal | ❌ |\n| `BRCS` | Branch if carry set | ❌ |\n| `BRCC` | Branch if carry cleared | ❌ |\n| `BRSH` | Branch if same or higher | ❌ |\n| `BRLO` | Branch if lower | ❌ |\n| `BRMI` | Branch if minus | ❌ |\n| `BRPL` | Branch if plus | ❌ |\n| `BRGE` | Branch if greater or equal (signed) | ❌ |\n| `BRLT` | Branch if less than (signed) | ❌ |\n| `BRHS` | Branch if half carry or carry set | ❌ |\n| `BRHC` | Branch if half carry or carry cleared | ❌ |\n| `BRTS` | Branch if T flag set | ❌ |\n| `BRTC` | Branch if T flag cleared | ❌ |\n| `BRVS` | Branch if overflow set | ❌ |\n| `BRVC` | Branch if overflow cleared | ❌ |\n| `BRIE` | Branch if interrupt enabled | ❌ |\n| `BRID` | Branch if interrupt disabled | ❌ |\n\n## Data transfer instructions\n\n| mnemonic | description | status |\n| --- | --- | --- |\n| `MOV` | Copy register | ❌ |\n| `MOVW` | Copy register pair | ❌ |\n| `LDI` | Load immediate | ❌ |\n| `LDS` | Load direct from data space | ❌ |\n| `LD` | Load indirect from data space | ❌ |\n| `LDD` | Load indirect with displacement | ❌ |\n| `STS` | Store direct to data space | ❌ |\n| `ST` | Store indirect to data space | ❌ |\n\n## Bit and bit-test instructions\n\n| mnemonic | description | status |\n| --- | --- | --- |\n| `LSL` | Logical shift left | ❌ |\n| `LSR` | Logical shift right | ❌ |\n| `ROL` | Rotate left through carry | ❌ |\n| `ROR` | Rotate right through carry | ❌ |\n| `ASR` | Arithmetic shift right | ❌ |\n| `SWAP` | Swap nibbles | ❌ |\n| `SBI` | Set bit in I/O register | ❌ |\n| `CBI` | Clear bit in I/O register | ❌ |\n| `BST` | Bit store from register to T | ❌ |\n| `BLD` | Bit load from T to register | ❌ |\n| `BSET` | Flag set | ❌ |\n| `BCLR` | Flag clear | ❌ |\n| `SEC` | Set carry flag | ❌ |\n| `CLC` | Clear carry flag | ❌ |\n| `SEN` | Set negative flag | ❌ |\n| `CLN` | Clear negative flag | ❌ |\n| `SEZ` | Set zero flag | ❌ |\n| `CLZ` | Clear zero flag | ❌ |\n| `SEI` | Set interrupt flag | ❌ |\n| `CLI` | Clear interrupt flag | ❌ |\n| `SES` | Set signed flag | ❌ |\n| `CLS` | Clear signed flag | ❌ |\n| `SEV` | Set overflow flag | ❌ |\n| `CLV` | Clear overflow flag | ❌ |\n| `SET` | Set T flag | ❌ |\n| `CLT` | Clear T flag | ❌ |\n| `SEH` | Set half carry flag | ❌ |\n| `CLH` | Clear half carry flag | ❌ |\n\n## MCU control instructions\n\n| mnemonic | description | status |\n| --- | --- | --- |\n| `BREAK` | Break | ✅ |\n| `NOP` | No operation | ✅ |\n| `SLEEP` | Sleep | ❌ |\n| `WDR` | Watchdog reset | ❌ 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