{"id":26104356,"url":"https://github.com/aolofsson/awesome-hardware-tools","last_synced_at":"2025-03-09T21:01:49.775Z","repository":{"id":37912859,"uuid":"479118982","full_name":"aolofsson/awesome-opensource-hardware","owner":"aolofsson","description":"List of awesome open source hardware tools, generators, and reusable designs","archived":false,"fork":false,"pushed_at":"2024-08-31T12:15:36.000Z","size":99,"stargazers_count":1891,"open_issues_count":5,"forks_count":172,"subscribers_count":69,"default_branch":"main","last_synced_at":"2024-10-29T17:56:05.030Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/aolofsson.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-04-07T19:18:24.000Z","updated_at":"2024-10-29T02:45:13.000Z","dependencies_parsed_at":"2024-02-29T00:22:54.434Z","dependency_job_id":"65f2571f-23d6-4251-989f-a897a2277f95","html_url":"https://github.com/aolofsson/awesome-opensource-hardware","commit_stats":{"total_commits":90,"total_committers":29,"mean_commits":3.103448275862069,"dds":"0.37777777777777777","last_synced_commit":"2c4e221f05e1c1e7025a8c66f67906a3e8407d0f"},"previous_names":["aolofsson/awesome-hardware-tools"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aolofsson%2Fawesome-opensource-hardware","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aolofsson%2Fawesome-opensource-hardware/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aolofsson%2Fawesome-opensource-hardware/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aolofsson%2Fawesome-opensource-hardware/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/aolofsson","download_url":"https://codeload.github.com/aolofsson/awesome-opensource-hardware/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":242750785,"owners_count":20179257,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-03-09T21:01:24.464Z","updated_at":"2025-03-09T21:01:49.752Z","avatar_url":"https://github.com/aolofsson.png","language":"Python","funding_links":[],"categories":["Other Lists","Technical","Uncategorized","Others","Python","Digital focussed tools"],"sub_categories":["Julia Lists","awesome-*","Uncategorized"],"readme":"# awesome-opensource-hardware\n\nA curated list of awesome open source hardware tools, generators, and reusable designs.\n\n* Categorized\n* Alphabetical (per category)\n* Requirements\n  - link should be to source code repository\n  - open source projects only\n  - working projects only (not WIP/rusty)\n* One tag line sentence per project\n\n# Table of Contents\n\n## PDKs\n   * [Manufacturable PDKs](#manufacturable-pdks)\n   * [Virtual PDKs](#virtual-pdks)\n\n## Compilers\n  * [Build systems](#build-systems)\n  * [Circuit compilers](#circuit-compilers)\n  * [FPGA compilers](#fpga-compilers)\n  * [Layout compilers](#layout-compilers)\n\n## Project\n  * [Documentation](#documentation)\n\n## Design and Verification Tools\n  * [Benchmarks](#benchmarks)\n  * [Board design](#board-design)\n  * [Digital design](#digital-design)\n  * [FPGA design](#fpga-design)\n  * [Formal verification](#formal-verification)\n  * [Linters](#linters)\n  * [Register design](#register-design)\n  * [Schematics](#scehamtics)\n  * [Simulators](#simulators)\n  * [Verification frameworks](#verification-frameworks)\n  * [Physics](#physics)\n  * [Waveform Viewers](#waveform-viewers)\n\n## Designs \u0026 Generators\n  * [Accelerators](#accelerators)\n  * [AIB](#aib)\n  * [AXI](#axi)\n  * [Analog circuits](#analog-circuits)\n  * [Chip packaging](#chip-packages)\n  * [Boards](#board-designs)\n  * [Connectivity](#connectivity)\n  * [CPUs](#cpus)\n  * [FPGA architectures](#fpga-architectures)\n  * [Libraries](#libraries)\n  * [Memory](#memory)\n  * [Systems](#systems)\n\n## Education\n  * [Analog design](#analog-design)\n  * [ASIC design](#asic-design)\n  * [Digital design](#digital-design)\n  * [FPGA design](#fpga-design)\n\n# PDKs\n\n## Manufacturable PDKs\n\n* [gf180](https://github.com/google/gf180mcu-pdk)\n  * GlobalFoundries 180nm CMOS PDK\n* [sg13g2](https://github.com/IHP-GmbH/IHP-Open-PDK)\n  * IHP 130nm BiCMOS PDK\n* [sky130](https://github.com/google/skywater-pdk)\n  * Skywater 130nm CMOS PDK\n\n## Virtual PDKs\n* [asap7](https://github.com/The-OpenROAD-Project/asap7)\n  * Predictive 7nm PDK\n* [freepdk45](https://github.com/siliconcompiler/siliconcompiler/tree/main/third_party/pdks/virtual/freepdk45)\n  * Predictive 45nm PDK\n* [probe3.0](https://github.com/ABKGroup/PROBE3.0)\n  * Process/design DTCO path finding technology\n\n# AI\n\n* [AnalogCoder](https://github.com/laiyao1/AnalogCoder)\n * Analog Circuit Design via Training-Free Code Generation\n* [hagent](https://github.com/masc-ucsc/hagent)\n * hardware agent\n* [Masala-CHAI](https://github.com/jitendra-bhandari/Masala-CHAI)\n * Large-Scale SPICE Netlist Dataset for Analog Circuits\n\n\n\n# Compilers\n\n## Build Systems\n* [bazelhdl](https://github.com/hdl/bazel_rules_hdl)\n  * Bazel based hdl build system\n* [bender](https://github.com/pulp-platform/bender)\n  * Dependency management tool for hardware projects.\n* [chipyard](https://github.com/ucb-bar/chipyard)\n  * Agile RISC-V SoC Design Framework.\n* [cocoon](https://github.com/pku-dasys/cocoon)\n  * Infrastructure for integrated EDA\n* [edalize](https://github.com/olofk/edalize)\n  * Abstraction library for interfacing EDA tools.\n* [flgen](https://github.com/pezy-computing/flgen)\n  * Generate a filelist for EDA tools\n* [fusesoc](https://github.com/olofk/fusesoc)\n  * Package manager and build abstraction tool for FPGA/ASIC development.\n* [hammer](https://github.com/ucb-bar/hammer)\n  * Agile physical design component part of UC Berkeley Chipyard framework.\n* [hwtbuildsystem](https://github.com/Nic30/hwtBuildsystem)\n  * Library of utils for interaction with the vendor tools.\n* [mflowgen](https://github.com/mflowgen/mflowgen)\n  * Build-system generator for ASIC and FPGA design-space exploration.\n* [orbit](https://github.com/chaseruskin/orbit)\n  * Package manager and build tool for HDLs.\n* [siliconcompiler](https://github.com/siliconcompiler/siliconcompiler)\n  * Modular distributed build system for hardware\n* [SoCMake](https://github.com/HEP-SoC/SoCMake)\n  * Hardware and software build system and package manager based on CMake\n\n## Circuit Compilers\n* [abc](https://github.com/berkeley-abc/abc)\n  * System for sequential logic synthesis and formal verification\n* [act](https://github.com/asyncvlsi/act)\n  * Asynchronous circuit compiler tools\n* [aihwkit](https://github.com/IBM/aihwkit)\n  * IBM Analog Hardware Acceleration Kit\n* [amaranth](https://github.com/amaranth-lang/amaranth)\n  * Python based hardware design framework\n* [bigspicy](https://github.com/google/bigspicy)\n  * Tool for merging circuit descriptions\n* [bsc](https://github.com/B-Lang-org/bsc)\n  * Compiler, simulator, and tools for the Bluespec Hardware Description Language\n* [calyx](https://github.com/cucapra/calyx)\n  * Intermediate language and compilers that generate custom hardware accelerators\n* [chisel](https://github.com/chipsalliance/chisel3)\n  * Scala based hardware description language\n* [circt](https://github.com/llvm/circt)\n  * Circuit IR Compilers and Tools\n* [circuitgraph](https://github.com/circuitgraph/circuitgraph)\n  * Tools for working with circuits as graphs in python\n* [circuitops](https://github.com/NVlabs/CircuitOps)\n  * Infrastructure for dataset generation and model deployment in Generative AI\n* [clash](https://github.com/clash-lang/clash-compiler)\n  * Haskell to VHDL/Verilog/SystemVerilog compiler\n* [coreir](https://github.com/rdaly525/coreir)\n  * LLVM-style hardware compiler with first class support for generators\n* [dfiant](https://github.com/DFiantHDL/DFiant)\n  * Dataflow Hardware Description Language\n* [fault](https://github.com/AUCOHL/Fault)\n  * Design-for-testing (DFT) Solution\n* [finn](https://github.com/Xilinx/finn)\n  * Dataflow compiler for QNN inference\n* [firrtl](https://github.com/chipsalliance/firrtl)\n  * Intermediate Representation for RTL\n* [gamma](https://github.com/maestro-project/gamma)\n  * Optimizes mapping of DNN models on DNN Accelerators\n* [gamora](https://github.com/Yu-Utah/Gamora)\n  * Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks\n* [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin)\n  * VHDL synthesis (based on ghdl)\n* [halide](https://github.com/halide/Halide)\n  * Language for fast, portable data-parallel computation\n* [halide-to-hardware](https://github.com/StanfordAHA/Halide-to-Hardware)\n  * Hardware generator combining halide and coreir\n* [hastlayer](https://github.com/Lombiq/Hastlayer-SDK)\n  * VHDL generator from .NET languages (C#, F#, and others) and FPGA framework for .NET hardware acceleration\n* [hdl21](https://github.com/dan-fritchman/Hdl21)\n  * Hardware Description Library\n* [hdlconvertor](https://github.com/Nic30/hdlConvertor)\n  * Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4\n* [hs-to-coq](https://github.com/plclub/hs-to-coq)\n  * Convert Haskell source code to Coq source code\n* [ipyxact](https://github.com/olofk/ipyxact)\n  * Python-based IP-XACT parser\n* [livehd](https://github.com/masc-ucsc/livehd)\n  * Infrastructure for live interactive synthesis and simulation\n* [llhd](https://github.com/fabianschuiki/llhd)\n  * Intermediate representation for digital circuit descriptions\n* [lsoracle](https://github.com/lnis-uofu/LSOracle)\n  * Famework built on EPFL logic synthesis libraries.\n* [lstools](https://github.com/lsils/lstools-showcase)\n  * Showcase examples for EPFL logic synthesis libraries\n* [kami](https://github.com/mit-plv/kami)\n  * Platform for High-Level Parametric Hardware Specification and Verification\n* [magma](https://github.com/phanrahan/magma/)\n  * Python based hardware design language\n* [matchlib](https://github.com/NVlabs/matchlib)\n  * Synthesizable SystemC/C++ library of commonly-used hardware functions\n* [matchclib_connections](https://github.com/hlslibs/matchlib_connections)\n  * Synthesizable SystemC library implementing latency-insensitive channels\n* [mockturtle](https://github.com/lsils/mockturtle)\n  * C++ logic network library\n* [myhdl](https://github.com/myhdl/myhdl)\n  * Python based hardware description and verification language\n* [naja](https://github.com/xtofalex/naja)\n  * Structural Netlist API for EDA post synthesis flow development\n* [netlist-paths](https://github.com/jameshanlon/netlist-paths)\n  * A library and command-line tool for querying a Verilog netlist\n* [panda-bambu](https://github.com/ferrandi/PandA-bambu)\n  * High level synthesis (HLS) C/C++ framework\n* [pipelinec](https://github.com/JulianKemmerer/PipelineC)\n  * C-like hardware description language (HDL) with automatic pipelining\n* [pygears](https://github.com/bogdanvuk/pygears)\n  * Python based hardware design framework\n* [pymtl3](https://github.com/pymtl/pymtl3)\n  * Python hardware generation, simulation, and verification framework\n* [pyrtl](https://github.com/UCSBarchlab/PyRTL)\n  * Python integrated design and simulation framework\n* [pysysc](https://github.com/accellera-official/PySysC)\n  * Python package to make SystemC usable from Python\n* [pyverilog](https://github.com/PyHDI/Pyverilog)\n  * Python design toolkit for Verilog HDL\n* [rohd](https://github.com/intel/rohd)\n  * Dart based framework for describing and verifying hardware\n* [scip](https://github.com/scipopt/scip)\n  * Solving Constraint Integer Problems\n* [silice](https://github.com/sylefeb/Silice)\n  * Language that simplifies prototyping and writing algorithms on FPGA architectures\n* [skidl](https://github.com/devbisme/skidl)\n  * SKiDL is a module that extends Python with the ability to design electronic circuits\n* [slang](https://github.com/MikePopoloski/slang)\n  * Library for lexing, parsing, type checking, and elaborating SystemVerilog code\n* [sodaopt](https://github.com/pnnl/soda-opt)\n  * Optimizer leveraging mlir to extract, optimize, translate HLSinto LLVM IR\n* [spinalhdl](https://github.com/SpinalHDL/SpinalHDL)\n  * Scala based HDL\n* [spydrnet](https://github.com/byuccl/spydrnet)\n  * Framework for analyzing and transforming Verilog netlists\n* [surelog](https://github.com/chipsalliance/Surelog)\n  * SystemVerilog IEEE 2017 Pre-processor, Parser, Elaborator, UHDM Compiler\n* [sv-parser](https://github.com/dalance/sv-parser)\n  * SystemVerilog IEEE 1800-2017 parser library\n* [sv2v](https://github.com/zachjs/sv2v)\n  * SystemVerilog to Verilog conversion\n* [systemc](https://github.com/accellera-official/systemc)\n  * SystemC system design and verification language that spans hardware and software\n* [systemc-compiler](https://github.com/intel/systemc-compiler)\n  * Translates synthesizable SystemC to synthesizable Verilog\n* [synlig](https://github.com/chipsalliance/synlig)\n  * SystemVerilog support for Yosys\n* [tapasco](https://github.com/esa-tu-darmstadt/tapasco)\n  * Heterogeneous system composer\n* [tce](https://github.com/cpc/tce)\n  * Application-specific instruction-set processor (ASIP) toolset\n* [uhdm](https://github.com/chipsalliance/UHDM)\n  * Universal object model for IEEE SystemVerilog designs\n* [verible](https://github.com/chipsalliance/verible)\n  * SystemVerilog developer tools, including a parser, style-linter, and formatter\n* [veriloggen](https://github.com/PyHDI/veriloggen)\n  * Mixed-Paradigm Hardware Construction Framework\n* [veryl](https://github.com/veryl-lang/veryl)\n  * Modern Hardware Description Language based on Rust/SV\n* [verik](https://github.com/frwang96/verik)\n  * Kotlin based hardware description language\n* [vlsir](https://github.com/Vlsir/Vlsir)\n  * Interchange formats for chip design\n* [xls](https://github.com/google/xls)\n  * Google framework for hardware synthesis\n* [yosys](https://github.com/YosysHQ/yosys)\n  * Yosys Open SYnthesis Suite\n\n## FPGA Compilers\n\n* [amf-placer](https://github.com/zslwyuan/AMF-Placer)\n  * Timing-driven analytical mixed-size FPGA placer\n* [dreamplacefpga](https://github.com/rachelselinar/DREAMPlaceFPGA)\n  * Analytical Placer for Large Scale Heterogeneous FPGA\n* [flowtune](https://github.com/Yu-Utah/FlowTune)\n  * FPGA synehsis and PNR optimizer\n* [nextpnr](https://github.com/YosysHQ/nextpnr)\n  * FPGA place and route tool\n* [vtr](https://github.com/verilog-to-routing/vtr-verilog-to-routing)\n  * FPGA place and route tool\n\n## Layout Compilers\n\n* [align](https://github.com/ALIGN-analoglayout/ALIGN-public)\n  * Automatic layout generator for analog circuits\n* [autodmp](https://github.com/NVlabs/AutoDMP)\n  * Automated DREAMPlace-based Macro Placement\n* [bag](https://github.com/ucb-art/BAG_framework)\n  * Berkeley analog layout generator\n* [coriolis](https://gitlab.lip6.fr/vlsi-eda/coriolis.git)\n  * RTL2GDS toolchain for mature nodes\n* [dreamplace](https://github.com/limbo018/DREAMPlace)\n  * Deep learning toolkit-enabled VLSI placement\n* [gdsfactory](https://github.com/gdsfactory/gdsfactory)\n  * Platform for chip design and layout\n* [gds3d](https://github.com/trilomix/GDS3D)\n  * Render GDS files in 3D\n* [gdsiistl](https://github.com/dteal/gdsiistl)\n  * Converts GDSII files to STL files\n* [gdstk](https://github.com/heitzmann/gdstk)\n  * C++/Python library for creation and manipulation of GDSII and OASIS files.\n* [gdspy](https://github.com/heitzmann/gdspy)\n  * Python module for creating GDSII stream files, usually CAD layouts.\n* [ieda](https://github.com/OSCC-Project/iEDA)\n  * RTL2GDS infrastructure\n* [klayout](https://github.com/KLayout/klayout)\n  * Layout viewer\n* [kweb](https://github.com/gdsfactory/kweb)\n  * Klayout Web Viewer\n* [lclayout](https://codeberg.org/librecell/lclayout)\n  * Layout generator for CMOS standard-cells\n* [layout21](https://github.com/dan-fritchman/Layout21)\n  * Integrated Circuit Layout\n* [magic](https://github.com/RTimothyEdwards/magic)\n  * Magic VLSI layout tool\n* [magical](https://github.com/magical-eda/MAGICAL)\n  * Machine Generated Analog IC Layout\n* [openroad](https://github.com/The-OpenROAD-Project/OpenROAD)\n  * Complete RTL2GDS platform\n* [phidl](https://github.com/amccaugh/phidl)\n  * Python GDS layout and CAD geometry creation\n\n\n# Design and Verification Tools\n\n## Benchmarks\n* [big-doe-openroad](https://github.com/msaligane/Big-DoE-OpenROAD)\n  * Framework for launching massive RTL2GDS experiements\n* [bringup-bench](https://github.com/toddmaustin/bringup-bench)\n  * Collection of minimal programs useful for system bringup\n* [bsg_pipeclean_suite](https://github.com/bespoke-silicon-group/bsg_pipeclean_suite)\n  * Collection of designs used to stress test new CAD flows\n* [corescore](https://github.com/olofk/corescore)\n  * Benchmark for FPGAs and their synthesis/P\u0026R tools\n* [epfl-benchmarks](https://github.com/lsils/benchmarks)\n  * Combinational Benchmark Suite for logic synthesis\n* [fpga-tool-perf](https://github.com/chipsalliance/fpga-tool-perf)\n  * FPGA tool performance profiling\n* [opdb](https://github.com/PrincetonUniversity/OPDB)\n  * Princeton design benchmark generators\n* [rdf-2020](https://github.com/ieee-ceda-datc/RDF-2020)\n  * IEEE CEDA eda benchmark flow\n* [sv-tests](https://github.com/chipsalliance/sv-tests)\n  * SystemVerilog compliance test suite\n* [verilog-eval](https://github.com/NVlabs/verilog-eval)\n  * Verilog evaluation benchmark for large language model\n\n## Board Design\n* [boardview](https://github.com/whitequark/kicad-boardview)\n  * Reads KiCAD PCB layout files and writes ASCII Boardview files\n* [cuflow](https://github.com/jamesbowman/cuflow)\n  * Experimental procedural PCB layout program\n* [datasheet-scrubber](https://github.com/idea-fasoc/datasheet-scrubber)\n  * Utility that scrubs PDF datasheets/documents in order to extract key circuit information\n* [freecad](https://github.com/FreeCAD/FreeCAD)\n  * 3D parametric CAD for building models of components for KiCad 3D preview (also enclosures)\n* [freerouting](https://github.com/freerouting/freerouting)\n  * PCB auto-router\n* [kicad](https://github.com/KiCad/kicad-source-mirror)\n  * Board design framework\n* [kicad-skip](https://github.com/psychogenic/kicad-skip)\n  * kicad s-expression schematic/layout file manipulation\n* [kicanvas](https://github.com/theacodes/kicanvas)\n  * KiCAD web viewer\n* [kicad-footprint-generator](https://gitlab.com/kicad/libraries/kicad-footprint-generator)\n  * kicad footprint generator using python scripts\n* [kicad-library-utils](https://gitlab.com/kicad/libraries/kicad-library-utils)\n  * scripts for helping with library development\n* [kikit](https://github.com/yaqwsx/KiKit)\n  * Automation tools for kicad\n* [librepcb](https://github.com/LibrePCB/LibrePCB)\n  * Board design framework\n* [pcbflow](https://github.com/michaelgale/pcbflow)\n  * Python based Printed Circuit Board (PCB) layout and design package based on CuFlow\n\n## Digital Design\n* [digital](https://github.com/hneemann/Digital)\n  * Digital logic designer and circuit simulator\n* [DigSim](https://github.com/freand76/digsim)\n  * An interactive digital logic simulator with verilog support (Yosys)\n* [verilog-mode](https://www.veripool.org/verilog-mode/)\n  * Popular free Verilog mode for Emacs\n* [vsrtl](https://github.com/mortbopet/VSRTL/)\n  * Visual Simulation of Register Transfer Logic\n* [vscode-systemverilog](https://github.com/eirikpre/VSCode-SystemVerilog)\n  * SystemVerilog support in VS Code\n* [vscode-teroshdl](https://github.com/TerosTechnology/vscode-terosHDL)\n  * Full IDE for RTL development in VS Code\n\n## Documentation\n* [elk](https://github.com/eclipse/elk)\n  * Eclipse Layout Kernel - Automatic layout for Java applications.\n* [graphviz](https://github.com/xflr6/graphviz)\n  * Python library for graph cration and rendering in DOT language\n* [gds3d](https://github.com/trilomix/GDS3D)\n  * Reads GDSII layout and renders in 3D\n* [hdelk](https://github.com/davidthings/hdelk)\n  * Web-based HDL diagramming tool\n* [kythe](https://github.com/chipsalliance/verible/blob/master/verilog/tools/kythe)\n  * Verible based SystemVerilog source file indexer\n* [memory-layout-diagram](https://github.com/gerph/memory-layout-diagram)\n  * Diagrams for memory map layouts\n* [netlistsvg](https://github.com/nturley/netlistsvg)\n  * Draws an SVG schematic from a JSON netlist\n* [netlist-viewer](https://github.com/f18m/netlist-viewer)\n  * SPICE netlist visualizer\n* [nn-svg](https://github.com/alexlenail/NN-SVG)\n  * Publication-ready NN-architecture schematics\n* [pcbdraw](https://github.com/yaqwsx/PcbDraw)\n  * Convert KiCAD board into 2D drawing suitable for pinout diagrams\n* [pinion](https://github.com/yaqwsx/Pinion)\n  * Generate interactive Diagrams for your PCBs\n* [pinout](https://github.com/j0ono0/pinout)\n  * Python package that generates hardware pinout diagrams as SVG images\n* [sphinx](https://github.com/sphinx-doc/sphinx)\n  * Document builder\n* [sphinx-verilog-domain](https://github.com/SymbiFlow/sphinx-verilog-domain)\n  * Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.\n* [sphinxcontrib-hdl-diagrams](https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams)\n  * Sphinx plugin to automatically generate diagrams from RTL.\n* [symbolator](https://github.com/kevinpt/symbolator)\n  * HDL symbol generator\n* [undulate](https://github.com/LudwigCRON/undulate)\n  * Python compatible wavedrom module with extensions and console rendering support\n* [wavedrom](https://github.com/wavedrom/wavedrom)\n  * Digital timing diagram rendering engine\n* [wavedrompy](https://github.com/wallento/wavedrompy)\n  * Python comptabled Wavedrom module\n* [wireviz](https://github.com/wireviz/WireViz)\n  * Docuyment cables and wiring harnesses\n\n\n## FPGA Design\n* [byteman](https://github.com/FPGA-Research-Manchester/byteman)\n  * Bitstream relocation and manipulation tool\n* [icestudio](https://github.com/FPGAwars/icestudio)\n  * Visual editor for open FPGA boards\n* [f4fpga](https://github.com/chipsalliance/f4pga)\n  * FPGA toolchain\n* [foedag](https://github.com/os-fpga/FOEDAG)\n  * Framework Open EDA Gui\n* [logik](https://github.com/zeroasiccorp/logik)\n  * FPGA toolchain\n* [openfpgaloader](https://github.com/trabucayre/openFPGALoader)\n  * Universal utility for programming FPGA\n* [rphax](https://github.com/shariethernet/RPHAX)\n  * Automation flow to develop and prototype hardware accelerators on Xilinx FPGAs\n\n## Formal Verification\n* [boolector](https://github.com/boolector/boolector)\n  * SMT solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions\n* [cvc5](https://github.com/cvc5/cvc5)\n  * SMT automatic theorem prover\n* [ilang](https://github.com/PrincetonUniversity/ILAng)\n  * Princeton modeling and Verification Platform for SoCs using ILAs\n* [autosva](https://github.com/PrincetonUniversity/AutoSVA)\n  * Generates FV testbenches and SVA properties for RTL modules based on interface annotations + GPT4\n* [autocc](https://github.com/morenes/AutoCC)\n  * A frontend for JG/SBY to automatically discover covert channels in time-shared hardware\n* [pono](https://github.com/upscale-project/pono)\n  * Extensible SMT-based model checker implemented in C++.\n* [sby](https://github.com/YosysHQ/sby)\n  * Front-end for Yosys-based formal verification flows.\n* [z3](https://github.com/Z3Prover/z3)\n  * Microsoft research theorem prover\n\n## Linters\n* [svlint](https://github.com/dalance/svlint)\n  * SystemVerilog linter\n* [svlint-action](https://github.com/dalance/svlint-action)\n  * GitHub action for svlint\n* [verible](https://github.com/chipsalliance/verible)\n  * SystemVerilog developer tools, including a parser, style-linter, and formatter\n* [verilator](https://github.com/verilator/verilator)\n  * SystemVerilog simulator and lint system\n\n## Register Design\n* [gen_registers](https://github.com/lsteveol/gen_registers)\n  * Python based tool for generating hardware registers and their associated files\n* [hdl-registers](https://github.com/hdl-registers/hdl-registers)\n  * Fast HDL register code generator\n* [rggen](https://github.com/rggen/rggen)\n  * Configuration and status register generator\n* [open-register-design-tool](https://github.com/Juniper/open-register-design-tool)\n  * Generate register RTL, models, and docs using SystemRDL or JSpec input\n* [peakrdl](https://github.com/SystemRDL/PeakRDL)\n  * SystemRDL based control \u0026 status register (CSR) toolchain\n* [systemrdl](https://github.com/SystemRDL/systemrdl-compiler)\n  * Generic compiler front-end for Accellera's SystemRDL 2.0 register description language\n\n## Schematics\n* [d3-hwschematics](https://github.com/Nic30/d3-hwschematic)\n  * Schematic visualizer\n* [kaktus2dev](https://github.com/kactus2/kactus2dev)\n  * Graphical EDA tool based on the IP-XACT standard\n* [openplc_editor](https://github.com/thiagoralves/OpenPLC_Editor)\n  * IDE capable of creating programs for the OpenPLC Runtime\n* [oregano](https://github.com/drahnr/oregano)\n  * Schematic capture and circuit simulator\n* [qucs_s](https://github.com/ra3xdh/qucs_s)\n  * Integrated circuit simulator with Graphical User Interface\n* [hdl21schematics](https://github.com/Vlsir/Hdl21Schematics)\n  * Hdl21 Schematics\n* [xschem](https://github.com/StefanSchippers/xschem)\n  * Schematic editor for VLSI/Asic/Analog custom designs\n\n## Electronics Simulators\n* [champsim](https://github.com/ChampSim/ChampSim)\n  * Trace-based simulator for a microarchitecture study\n* [dromajo](https://github.com/chipsalliance/dromajo)\n  * RISC-V RV64GC functional emulator\n* [eesim](https://github.com/danchitnis/EEsim)\n  * Browser-based SPICE circuit simulator\n* [essent](https://github.com/ucsc-vama/essent)\n  * High-performance FIRRTL (Chisel) simulator\n* [firesim](https://github.com/firesim/firesim)\n  * FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud\n* [gem5](https://github.com/gem5/gem5)\n  * Modular simulator platform for computer-system architecture research\n* [muchisim](https://github.com/PrincetonUniversity/muchisim)\n  * Cycle-level simulator for PPA and cost analysis of distributed multi-chiplet tile-based manycore designs.\n* [ghdl](https://github.com/ghdl/ghdl)\n  * VHDL 2008/93/87 simulator\n* [icarus](https://github.com/steveicarus/iverilog.git)\n  * Verilog IEEE-1364 simulator\n* [irsim](https://github.com/RTimothyEdwards/irsim)\n  * Switch-level simulator for digital circuits\n* [libsystemctlm-soc](https://github.com/Xilinx/libsystemctlm-soc)\n  * SystemC/TLM-2.0 Co-simulation framework\n* [logisim-evolution](https://github.com/logisim-evolution/logisim-evolution)\n  * Digital logic design tool and simulator\n* [lwtr4sc](https://github.com/Minres/LWTR4SC)\n  * Transaction recording for SystemC\n* [ngspice](http://ngspice.sourceforge.net/)\n  * Spice simulator\n* [noxim](https://github.com/davidepatti/noxim)\n  * Network on Chip Simulator\n* [nvc](https://github.com/nickg/nvc)\n  * VHDL compiler and simulator\n* [pysysc](https://github.com/accellera-official/PySysC)\n  * Python package to make SystemC usable from Python\n* [qemu](https://github.com/qemu/qemu)\n  * Generic and open source machine \u0026 userspace emulator and virtualizer\n* [ramulator2](https://github.com/CMU-SAFARI/ramulator2)\n  * Cycle accurate DRAM simulator\n* [renode](https://github.com/renode/renode)\n  * Generic and open source machine emulator\n* [sax](https://github.com/flaport/sax)\n  * S-parameter based frequency domain circuit simulation\n* [SimEng](https://github.com/UoB-HPC/SimEng)\n  * Fast, easily modifiable, cycle-level CPU simulator framework supporting RV64 and AArch64—integrating with SST\n* [simulide](https://github.com/SimulIDE/SimulIDE)\n  * SimulIDE is a simple real-time electronic circuit simulator\n* [SST](https://github.com/sstsimulator/sst-core)\n  * Simulation platform to connect multiple simulated hardware objects\n* [systemc-components](https://github.com/Minres/SystemC-Components)\n  * SystemC simulation productivity library\n* [tiny-five](https://github.com/OpenMachine-ai/tinyfive)\n  * Lightweight RISC-V emulator and assembler written entirely in Python with examples for AI/ML\n* [xictools](https://github.com/wrcad/xictools)\n  * Circuit simulation package\n* [xyce](https://github.com/Xyce/Xyce)\n  * Parallel spice simulator from Sandia national labs\n* [verilator](https://github.com/verilator/verilator)\n  * SystemVerilog simulator and lint system\n\n## Verification Frameworks\n* [adc-eval](https://github.com/esynr3z/adc-eval)\n  * Python tools for ADC performance analysis\n* [awsteria_infra](https://github.com/bluespec/AWSteria_Infra)\n  * Middleware for AWS hosted FPGA applications\n* [anasysmod](https://github.com/sgherbst/anasymod)\n  * Framework for FPGA emulation of mixed-signal systems\n* [cocotb](https://github.com/cocotb/cocotb)\n  * Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python\n* [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi)\n  * AXI interface modules for Cocotb\n* [cocotbext-pcie](https://github.com/alexforencich/cocotbext-pcie)\n  * PCI express simulation framework for Cocotb\n* [constrainedrandom](https://github.com/imaginationtech/constrainedrandom)\n  * Python package for creating and solving constrained randomization problems\n* [cvc](https://github.com/d-m-bailey/cvc)\n  * CVC: Circuit Validity Checker\n* [core-v-verif](https://github.com/openhwgroup/core-v-verif)\n  * Functional verification project for the CORE-V family of RISC-V cores\n* [ddr5_phy](https://github.com/Shehab-Naga/ddr5_phy)\n  * UVM testbench for DDR5 PHY\n* [fault](https://github.com/leonardt/fault)\n  * Python package for testing hardware\n* [force-riscv](https://github.com/openhwgroup/force-riscv)\n  * Instruction Set Generator for RISC-V\n* [frame](https://github.com/maestro-project/frame)\n  * Fast Roofline Analytical Modeling and Estimation\n* [fstdumper](https://github.com/semify-eda/fstdumper)\n  * Verilog VPI module to dump FST (Fast Signal Trace) databases\n* [lctime](https://codeberg.org/librecell/lctime)\n  * Library cell characterization\n* [maestro](https://github.com/maestro-project/maestro)\n  * Analytical cost model evaluating DNN mappings (dataflows and tiling)\n* [msdsl](https://github.com/sgherbst/msdsl)\n  * Automatic generation of real number models from analog circuits\n* [netgen](https://github.com/RTimothyEdwards/netgen)\n  * LVS tool for comparing SPICE or verilog netlists\n* [openplc_v3](https://github.com/thiagoralves/OpenPLC_v3)\n  * OpenPLC Runtime version 3\n* [opensta](https://github.com/The-OpenROAD-Project/OpenSTA)\n  * Signoff quality STA engine used by OpenRoad\n* [opentimer](https://github.com/OpenTimer/OpenTimer)\n  * High performance static timing analysis\n* [openvaf](https://github.com/pascalkuthe/OpenVAF)\n  * Next generation Verilog-A compiler\n* [osvvm](https://github.com/OSVVM/OsvvmLibraries)\n  * A VHDL verification framework\n* [pcievhost](https://github.com/wyvernSemi/pcievhost)\n  * PCIe (1.0a to 2.0) Virtual host model for verilog\n* [pyspice](https://github.com/PySpice-org/PySpice)\n  * Python interface for ngspice and xyce\n* [pyucis](https://github.com/fvutils/pyucis)\n  * Python API to Unified Coverage Interoperability Standard (UCIS) Data\n* [pyuvm](https://github.com/pyuvm/pyuvm)\n  * SystemVerilog UVM written in Python\n* [pyvsc](https://github.com/fvutils/pyvsc)\n  * Python packages or SystemVerilog UVM style Verification Stimulus and Coverage\n* [raft](https://github.com/Xilinx/RAFT)\n  * Rapid Abstraction FPGA Toolbox\n* [riscv-dv](https://github.com/chipsalliance/riscv-dv)\n  * Random instruction generator for RISC-V processor verification\n* [rohd-cosim](https://github.com/intel/rohd-cosim)\n  * Framework for cosimulation between the ROHD simulator and SystemVerilog simulators.\n* [rohd-vf](https://github.com/intel/rohd-vf)\n  * ROHD-based verification and testbench framework in Dart.\n* [switchboard](https://github.com/zeroasiccorp/switchboard/)\n  * Communication framework for RTL simulation and emulation\n* [svreal](https://github.com/sgherbst/svreal)\n  * Synthesizable real number library in SystemVerilog (fixed \u0026 floating point formats)\n* [systemctlm-cosim-demo](https://github.com/Xilinx/systemctlm-cosim-demo)\n  * Demo system for libsystemctlm-soc library\n* [sv_waveterm](https://github.com/PeterMonsson/sv_waveterm)\n  * Generate text waves in simulation log file\n\n* [uvvm](https://github.com/UVVM/UVVM)\n  * Library for making very structured VHDL-based testbenches.\n* [v2k-top](https://github.com/kev-cam/v2k-top)\n  * Parser/simulation framework for Verilog \u0026 C++\n* [vidbo](https://github.com/olofk/vidbo)\n  * Virtual development board\n* [vunit](https://github.com/VUnit/vunit)\n  * Unit testing framework for VHDL/SystemVerilog\n\n## Physics\n* [devsim](https://github.com/devsim)\n  * TCAD Semiconductor Device Simulator\n* [elmer](https://github.com/ElmerCSC/elmerfem)\n  * Finite Element Solver\n* [femwell](https://github.com/HelgeGehring/femwell)\n  * Finite element based simulation tool for integrated circuits, electric and photonic\n* [hotspot](https://github.com/uvahotspot/HotSpot)\n  * Thermal modeling tool for use in architectural studies\n* [meep](https://github.com/NanoComp/meep)\n  * Finite-difference-time-domain (FDTD) electromagneic simulation\n* [paraview](https://github.com/Kitware/ParaView)\n  * Data Analysis and Visualization Application\n* [pact](https://github.com/peaclab/PACT)\n  * Thermal simulator\n* [scikit-rf](https://github.com/scikit-rf/scikit-rf)\n  * RF and Microwave Engineering Scikit\n\n## Waveform Viewers\n* [scviewer](https://github.com/Minres/SCViewer)\n  * Eclipse plugins to display VCD (e.g. created by SystemC VCD trace).\n* [d3wave](https://github.com/Nic30/d3-wave)\n  * D3.js based wave (signal) visualizer\n* [gtkwave](https://github.com/gtkwave/gtkwave)\n  * GTK+ based VCD waveform viewer\n* [iio-oscilloscope](https://github.com/analogdevicesinc/iio-oscilloscope)\n  * GTK+ based oscilloscope application for interfacing with various IIO devices\n* [konata](https://github.com/shioyadan/Konata)\n  * Instruction pipeline visualizer for Gem5\n* [npTDMS](https://github.com/adamreeve/npTDMS)\n  * Python module for reading TDMS files produced by LabView\n* [scopy](https://github.com/analogdevicesinc/scopy)\n  * Software oscilloscope and signal analysis toolset\n* [sigrok](https://github.com/sigrokproject)\n  * Portable, signal analysis software suite (logic analyzers, scopes, multimeters, and more)\n* [simview](https://github.com/pieter3d/simview)\n  * Text-based SystemVerilog design browser and waveform viewer\n* [sootty](https://github.com/Ben1152000/sootty)\n  * Command-line tool for displaying vcd waveforms\n* [spyci](https://github.com/gmagno/spyci)\n  * Python package to parse spice raw data files\n* [verilog-vcd-parser](https://github.com/ben-marshall/verilog-vcd-parser)\n  * Parser for Value Change Dump (VCD) files\n* [wavebin](https://github.com/sam210723/wavebin)\n  * Oscilloscope waveform capture viewer and converter\n* [waveforms-live](https://github.com/Digilent/waveforms-live)\n  * Browser based analog waveform viewer\n\n# Designs \u0026 Generators\n\n## Accelerators\n* [aes](https://github.com/secworks/aes)\n  * Symmetric block cipher AES (Advanced Encryption Standard)\n* [ara](https://github.com/pulp-platform/ara)\n  * Vector Unit, compatible with the RISC-V Vector Extension\n* [bfg](https://github.com/growly/bfg)\n  * Compiler for Reduced-Complexity Reconfigurable Fabrics\n* [bismp](https://github.com/EECS-NTNU/bismo/)\n  * Chisel-based bit-serial matrix multiplication accelerator generator\n* [finn](https://github.com/Xilinx/finn)\n  * Quantized NN to FPGA dataflow accelerator generator\n* [fftgenerator](https://github.com/ucb-bar/FFTGenerator)\n  * MMIO-Based FFT Generator\n* [fpu](https://github.com/dawsonjon/fpu)\n  * Synthesizable ieee 754 floating point library in verilog\n* [garnet](https://github.com/StanfordAHA/garnet)\n  * CGRA generator\n* [gemmini](https://github.com/ucb-bar/gemmini)\n  * Berkeley Spatial Array Generator\n* [gplgpu](https://github.com/asicguy/gplgpu)\n  * GPL v3 2D/3D graphics engine in verilog\n* [core_jpeg](https://github.com/ultraembedded/core_jpeg)\n  * High throughput JPEG decoder in Verilog for FPGA\n* [fftgenerator](https://github.com/ucb-bar/FFTGenerator)\n  * Chisel based FFT generator\n* [h265-encoder-rtl](https://github.com/openasic-org/h265-encoder-rtl)\n  * H.265 Video Encoder IP Core\n* [logicnets](https://github.com/Xilinx/logicnets)\n  * Train and generate LUT-based neural networks\n* [nngen](https://github.com/NNgen/nngen)\n  * Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network\n* [nvdla](https://github.com/nvdla/hw)\n  * NVIDIA Deep Learning Accelerator (NVDLA)\n* [nyuziprocessor](https://github.com/jbush001/NyuziProcessor)\n  * GPGPU microprocessor architecture\n* [opencgra](https://github.com/pnnl/OpenCGRA)\n  * Parametrizable Coarse-Grained Reconfigurable Array (CGRA) Generator\n* [openofdm](https://github.com/jhshi/openofdm)\n  * 802.11 OFDM PHY decoder\n* [openspike](https://github.com/sfmth/OpenSpike)\n  * Spiking neural network accelerator\n* [project-zipline](https://github.com/opencomputeproject/Project-Zipline)\n  * Zipline lossless compression implementation\n* [pyfda](https://github.com/chipmuenk/pyFDA)\n  * Python Filter Design Analysis Tool\n* [ranc](https://github.com/UA-RCL/RANC)\n  * Reconfigurable architecture for neuromorphic computing\n* [sha256](https://github.com/secworks/sha256)\n  * SHA-256 hash function (NIST FIPS 180-4)\n* [sha512](https://github.com/secworks/sha512)\n  * SHA-512 hash function (NIST FIPS 180-4)\n* [sha3](https://github.com/ucb-bar/sha3)\n  * Berkeley SHAR3 ROCC Accelerator\n* [serpens](https://github.com/linghaosong/Serpens)\n  * HBM FPGA based SpMV Accelerator\n* [sextans](https://github.com/linghaosong/Sextans)\n  * FPGA accelerator for Sparse-Matrix Dense-Matrix Multiplication (SpMM)\n* [spiral](https://github.com/spiral-software/spiral-software)\n  * Spiral based FFT generator\n* [tvm-vta](https://github.com/apache/tvm-vta)\n  * Opwn, modular, deep learning accelerator\n* [verigood-ml](https://github.com/VeriGOOD-ML/public)\n  * Verilog Generator, Optimized for Designs for Machine Learning\n* [Viterbi](https://github.com/Archit-halder/Viterbi-Algorithm)\n  * Viterbi encoder/decoder (2,1,4)\n* [Viterbi](https://github.com/jfoshea/Viterbi-Decoder-in-Verilog)\n  * Viterbi decoder (2,1,3) (3,2,2) (2,1,3) (3,2,2)\n* [verigpu](https://github.com/hughperkins/VeriGPU)\n  * OpenSource GPU, loosely based on RISC-V ISA\n* [verilog-lfsr](https://github.com/alexforencich/verilog-lfsr)\n  * Parametrizable combinatorial parallel LFSR/CRC module\n* [vortex](https://github.com/vortexgpgpu/vortex)\n  * Full-system RISCV-based GPGPU processor\n\n## AIB\n* [aib](https://github.com/chipsalliance/aib-phy-hardware)\n  * Advanced Interface Bus (AIB) die to die hardware\n* [aib-protocols](https://github.com/chipsalliance/aib-protocols)\n  * Advanced Interface Bus (AIB) Protocol IP\n* [axi4_aib_bridge](https://github.com/lmco/axi4_aib_bridge)\n  * AXI4/AIB Bridge RTL\n\n## AXI\n* [axi](https://github.com/pulp-platform/axi)\n  * (Pulp) AXI SystemVerilog synthesizable IP\n* [axi-crossbar](https://github.com/dpretet/axi-crossbar)\n  * AXI4 crossbar implemented in SystemVerilog\n* [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi)\n  * AXI interface modules for Cocotb\n* [tvip-apb](https://github.com/taichi-ishitani/tvip-apb)\n  * UVM based AMBA APB VIP\n* [tvip-axi](https://github.com/taichi-ishitani/tvip-axi)\n  * UVM based AMBA AXI VIP\n* [verilog-axis](https://github.com/alexforencich/verilog-axis)\n  * (Forencich) Verilog AXI stream components for FPGA implementation\n* [wb2axip](https://github.com/ZipCPU/wb2axip)\n  * AXI-Wishbone bus bridges\n\n## Analog Circuits\n* [ams_kgd](https://github.com/USCPOSH/AMS_KGD)\n  * Repository for Known Good Analog Designs (KGDs)\n* [analog_blocks](https://github.com/mabrains/Analog_blocks)\n  * Basic building blocks (OTA, BandGap and LDO) in Skywater 130nm.\n* [openfasoc](https://github.com/idea-fasoc/OpenFASOC)\n  * Automated Mixed Signal SoC Synthesis Framework\n* [open-pmic](https://github.com/westonb/open-pmic)\n  * Current mode buck converter on the SKY130 PDK\n\n## Chip Packaging\n* [bsg_packaging](https://github.com/bespoke-silicon-group/bsg_packaging)\n  * Open-Source Hardware Accelerator Packages and Sockets\n\n## Boards\n* [bsg_motherboards](https://github.com/bespoke-silicon-group/bsg_motherboards)\n  * BaseJump Hardware Accelerator Motherboards\n* [gmm7550](https://github.com/ak-fau/gmm7550)\n  * CologneChip GateMate FPGA Module: GMM-7550\n* [google-coral-baseboard](https://github.com/antmicro/google-coral-baseboard)\n  * Open hardware baseboard for the Google Coral i.MX8 + Edge TPU SoM\n* [hardware-components](https://github.com/antmicro/hardware-components)\n  * Collection of KiCad components\n* [parallella-hw](https://github.com/parallella/parallella-hw)\n  * Collection of open source boards from Adapteva\n\n## Connectivity\n* [bsg_ddr3_io](https://github.com/bespoke-silicon-group/bsg_ddr3_io)\n  * BaseJump DDR3 I/O Design\n* [core_ddr3_controller](https://github.com/ultraembedded/core_ddr3_controller)\n  * DDR3 memory controller in Verilog for various FPGAs\n* [ctucanfd_ip_core](https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core)\n  * CAN with Flexible Data-rate IP Core developed at Department of Measurement of FEE CTU\n* [hdmi](https://github.com/hdl-util/hdmi)\n  * Send video/audio over HDMI on an FPGA\n* [i2c](https://github.com/hdl-util/i2c)\n  * Fully featured implementation of Inter-IC (I2C) bus master\n* [idma](https://github.com/pulp-platform/iDMA)\n  * Modular, parametrizable, and highly flexible Data Movement Accelerator\n* [io-gen](https://github.com/GT-CHIPS/IO-Gen)\n  * IO cell generator\n* [litedram](https://github.com/enjoy-digital/litedram)\n  * Small footprint and configurable DRAM (litex)\n* [liteeth](https://github.com/enjoy-digital/liteeth)\n  * Small footprint and configurable Ethernet core\n* [litescope](https://github.com/enjoy-digital/litescope)\n  * Small footprint and configurable embedded FPGA logic analyzer\n* [litepice](https://github.com/enjoy-digital/litepcie)\n  * Small footprint and configurable PCIe core\n* [nocrouter](https://github.com/agalimberti/NoCRouter)\n  * Network-on-Chip Router\n* [omi_device_ice](https://github.eom/OpenCAPI/omi_device_ice)\n  * Open memory interface example device\n* [opencapi_accel](https://github.com/OpenCAPI/oc-accel)\n  * OpenCAPI acceleration framework\n* [opencapi_client](https://github.com/OpenCAPI/OpenCAPI3.0_Client_RefDesign)\n  * OpenCAPI client reference design\n* [openserdes](https://github.com/SparcLab/OpenSERDES)\n  * Digitally synthesizable architecture for SerDes using Skywater130\n* [pymtl3-net](https://github.com/cornell-brg/pymtl3-net)\n  * Cornell parameterizable OCN (on-chip network) generator\n* [ravenoc](https://github.com/aignacio/ravenoc)\n  * Configurable HDL NoC (Network-On-Chip)\n* [tnoc](https://github.com/taichi-ishitani/tnoc)\n  * Network on Chip Implementation written in SytemVerilog\n* [usb3_camera](https://github.com/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3)\n  * USB C Industrial Camera Project\n* [usb_cdc](https://github.com/ulixxe/usb_cdc/)\n  * Minimal USB CDC (ACM) implementation in verilog\n* [usb_dfu](https://github.com/ulixxe/usb_dfu/tree/main)\n  * Verilog implementation of the USB Device Class Specification for Device Firmware Upgrade (DFU), version 1.1\n* [umi](https://github.com/zeroasiccorp/umi)\n  * Universal Memory Interface\n* [verilog-ethernet](https://github.com/alexforencich/verilog-ethernet)\n  * Verilog Ethernet components for FPGA implementation\n* [verilog-i2c](https://github.com/alexforencich/verilog-i2c)\n  * Verilog I2C interface for FPGA implementation\n* [verilog-uart](https://github.com/alexforencich/verilog-uart)\n  * Verilog UART\n* [verilog-pcie](https://github.com/alexforencich/verilog-pcie)\n  * Verilog PCI express components\n* [verilog-wishbone](https://github.com/alexforencich/verilog-wishbone)\n  * Verilog wishbone components\n* [vis4mesh](https://github.com/ueqri/vis4mesh)\n  * Visualization tool for designing mesh Network-on-Chips\n* [vivado-library](https://github.com/Digilent/vivado-library)\n  * IP cores and interface definitions compatible with Xilinx Vivado IP Catalog\n* [wav-d2d-hw](https://github.com/waviousllc/wav-d2d-hw)\n  * 8lane Wlink with D2D and a single AXI Target/Initiator\n* [wav-lpddr-hw](https://github.com/waviousllc/wav-lpddr-hw)\n  * DDR (WDDR) Physical interface (PHY) Hardware\n* [wav-slink-hw](https://github.com/waviousllc/wav-slink-hw)\n  * Chiplet link\n* [wav-wlink-hw](https://github.com/waviousllc/wav-wlink-hw)\n  * Chiplet link\n\n## CPUs\n* [a2i](https://github.com/openpower-cores/a2i)\n  * A2I POWER processor core RTL (VHDL)\n* [ara](https://github.com/pulp-platform/ara)\n  * 64-bit Vector unit coprocessor to Ccva6\n* [black-parrot](https://github.com/black-parrot/black-parrot)\n  * Linux-capable RISC-V multicore\n* [cfu-playground](https://github.com/google/CFU-Playground/)\n  * Famework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers\n* [cores-swerv](https://github.com/chipsalliance/Cores-SweRV)\n  * SweRV EH1 RISC-Vcore\n* [cores-swerv-el2](https://github.com/chipsalliance/Cores-SweRV-EL2)\n  * SweRV EL2 RISC-V Core\n* [core-v-verif](https://github.com/openhwgroup/core-v-verif)\n  * Functional verification project for the CORE-V family of RISC-V cores\n* [cva6](https://github.com/openhwgroup/cva6)\n  * Linux capable RISC-V CPU\n* [cve2](https://github.com/openhwgroup/cve2)\n  * Small two-stage 32 bit RISC-V CPU core (RV32IMC/EMC)\n* [cv32e40s](https://github.com/openhwgroup/cv32e40s)\n  * RV32IMFCX RISC-V 4-stage secure RISC-V CPU\n* [cv32e40x](https://github.com/openhwgroup/cv32e40x)\n  * RV32IMFCX RISC-V 4-stage compute RISC-V CPU\n* [cvw](https://github.com/openhwgroup/cvw)\n  * Configurable RISC-V Processor for RISC-V System-on-Chip Design textbook.\n* [ibex](https://github.com/lowRISC/ibex)\n  * Small 32 bit RISC-V CPU core\n* [lizard](https://github.com/cornell-brg/lizard)\n  * Cornell modular RV64IM Out-of-Order Processor Built with PyMTL\n* [microwatt](https://github.com/antonblanchard/microwatt)\n  * Open POWER ISA softcore written in VHDL 2008\n* [minimax](https://github.com/gsmecher/minimax)\n  * A Compressed-First, Microcoded RISC-V CPU\n* [muntjac](https://github.com/lowRISC/muntjac)\n  * Simple 64-bit RISC-V multicore processor\n* [neorv32](https://github.com/stnolting/neorv32)\n  * Customizable and highly extensible MCU-class 32-bit RISC-V (VHDL)\n* [openxiangshan](https://github.com/OpenXiangShan/XiangShan)\n  * Open-source high-performance RISC-V processor\n* [picorv32](https://github.com/YosysHQ/picorv32)\n  * Size-Optimized RISC-V CPU\n* [rocket-chip](https://github.com/chipsalliance/rocket-chip)\n  * Linux capable RISC-V Rocket Chip Generator\n* [rioschip](https://github.com/b224hisl/rioschip)\n  * Out of order RISC-V core\n* [serv](https://github.com/olofk/serv)\n  * SErial RISC-V CPU\n* [snitch](https://github.com/pulp-platform/snitch)\n  * Lean but mean RISC-V system\n* [veer](https://github.com/chipsalliance/Cores-VeeR-EL2)\n  * 32-bit integer machine-mode RISC-V CPU\n* [vroom](https://github.com/MoonbaseOtago/vroom)\n  * High performance RISC-V CPU\n\n## FPGA Architectures\n* [fabulous](https://github.com/FPGA-Research-Manchester/FABulous)\n  * Fabric generator and CAD tools\n* [fabric_team](https://github.com/ucb-cs250/fabric_team)\n  * Simple Berkeley FPGA generator class project\n* [openfpga](https://github.com/lnis-uofu/OpenFPGA)\n  * FPGA IP Generator\n* [prga](https://github.com/PrincetonUniversity/prga)\n  * Open-source FPGA research and prototyping framework\n\n## Libraries\n* [async_fifo](https://github.com/dpretet/async_fifo)\n  * Dual clock asynchronous FIFO\n* [basejump_stl](https://github.com/bespoke-silicon-group/basejump_stl)\n  * Library of SystemVerilog components\n* [basic_verilog](https://github.com/pConst/basic_verilog)\n  * Library of SystemVerilog components\n* [berkeley-hardfloat](https://github.com/ucb-bar/berkeley-hardfloat)\n  * Berkeley hardware floating point units\n* [common_cells](https://github.com/pulp-platform/common_cells)\n  * Library of SystemVerilog components\n* [cvfpu](https://github.com/openhwgroup/cvfpu)\n  * Parametric floating-point unit\n* [hdl](https://github.com/analogdevicesinc/hdl)\n  * Library of Analog Deveices specific components\n* [lambdalib](https://github.com/siliconcompiler/lambdalib)\n  * Hardware abstraction library\n* [lambdapdk](https://github.com/siliconcompiler/lambdapdk)\n  * Library of open source Process Design Kits (PDKs)\n* [libsv](https://github.com/bensampson5/libsv)\n  * Parameterized SystemVerilog digital hardware library\n* [mathlib](https://github.com/asfigo/mathlib)\n  * SystemVerilog MathLib\n* [oh](https://github.com/aolofsson/oh)\n  * Library of Verilog components\n* [Open Logic](https://github.com/open-logic/open-logic)\n  * Vendor Independent FPGA Standard Library with focus on quality (documentation, 100% test coverage, quality metrics)\n  * Written in VHDL but usable from Verilog as well (System Verilog tutorials available)\n* [pztb-core](https://github.com/pezy-computing/pztb-core)\n  * Collection of class libraries for testbench development\n* [pzbcm](https://github.com/pezy-computing/pzbcm)\n  * Basic common modules\n* [rohd-hcl](https://github.com/intel/rohd-hcl)\n  * Library of reusable \u0026 configurable hardware components developed with ROHD\n* [vlsiffra](https://github.com/antonblanchard/vlsiffra)\n  * Fast and efficient standard cell based adders, multipliers and multiply-adders\n\n## Memory\n* [core_axi_cache](https://github.com/ultraembedded/core_axi_cache)\n  * 128KB AXI cache (32-bit in, 256-bit out)\n* [cv-hpdcache](https://github.com/openhwgroup/cv-hpdcache)\n  * High-Performance L1 Dcache\n* [bsg_fakeram](https://github.com/bespoke-silicon-group/bsg_fakeram)\n  * Fake RAM generator\n* [huancun](https://github.com/OpenXiangShan/HuanCun)\n  * Open-source high-performance non-blocking cache\n* [openram](https://github.com/VLSIDA/OpenRAM)\n  * Static random access memory (SRAM) compiler.\n* [lake](https://github.com/StanfordAHA/lake)\n  * Synthesizable memory generator\n\n## Systems\n* [caliptra](https://github.com/chipsalliance/caliptra)\n  * Caliptra Root of Trust Architecture\n* [caliptra-rtl](https://github.com/chipsalliance/caliptra-rtl)\n  * Caliptra Root of Trust (RTL)\n* [beagle_sdr_gps](https://github.com/jks-prv/Beagle_SDR_GPS)\n  * KiwiSDR: BeagleBone web-accessible GPS/SDR\n* [bsg_manycore](https://github.com/bespoke-silicon-group/bsg_manycore)\n  * Tile based architecture designed for computing efficiency, scalability\n* [cep](https://github.com/CommonEvaluationPlatform/CEP)\n  * RISC-V based Common Evaluation Platform (CEP)\n* [esp](https://github.com/sld-columbia/esp)\n  * Heterogeneous SoC architecture and IP design platform\n* [falcon](https://github.com/falkenber9/falcon)\n  * Fast Analysis of LTE Control channels\n* [hero](https://github.com/pulp-platform/hero)\n  * FPGA-based research platform for heterogeneous design\n* [litex](https://github.com/enjoy-digital/litex)\n  * SoC builder framework\n* [openfasoc](https://github.com/idea-fasoc/OpenFASOC)\n  * Open Source FASOC generators\n* [openpiton](https://github.com/PrincetonUniversity/openpiton)\n  * General purpose, multithreaded manycore processor\n* [opentitan](https://github.com/lowRISC/opentitan)\n  * Open source silicon root of trust\n* [openwifi-hw](https://github.com/open-sdr/openwifi-hw)\n  * IEEE 802.11 WiFi baseband FPGA (chip) design\n* [pulp](https://github.com/pulp-platform/pulp)\n  * Multicore RISC-V based SoC\n* [pulpissimo](https://github.com/pulp-platform/pulpissimo)\n  * Single core RISC-V based SoC\n* [rose](https://github.com/ucb-bar/RoSE)\n  * Unified simulation platform for robotic systems\n* [senseq](https://github.com/EMIL-YORKU/SensSeq)\n  * Mixed-signal system on chip for nanopore-based DNA sequencing\n* [verilogboy](https://github.com/zephray/VerilogBoy)\n  * Game Boy compatible machine with Verilog\n* [wulpus](https://github.com/pulp-bio/wulpus)\n  * Wearable low-power ultrasound probe\n* [x-heep](https://github.com/esl-epfl/x-heep)\n  * Extendable and configurable RISC-V SoC\n\n## Boards\n\n* [artix-dc-scm](https://github.com/antmicro/artix-dc-scm)\n  * Antmicro OCP data center secure control module\n* [arty-mpw-tester](https://github.com/antmicro/arty-mpw-tester)\n  * Antmicro Caravel fanout board\n* [fomu](https://github.com/im-tomu/fomu-hardware)\n  * Tiny USB FPGA board\n* [icebreaker](https://github.com/icebreaker-fpga/icebreaker)\n  * Low cost FPGA development board\n* [lpddr5-testbed](https://github.com/antmicro/lpddr5-testbed)\n  * Antmicro lpddr5 testbed\n* [PicoEVB](https://github.com/RHSResearchLLC/PicoEVB)\n  * M.2 80mm Artix FPGA evaluation board\n* [qomu-dev-board](https://github.com/QuickLogic-Corp/qomu-dev-board)\n  * Quicklogic efpga USB dev board\n* [scalenode-cm4-baseboard](https://github.com/antmicro/scalenode-cm4-baseboard)\n  * Antmicro basedboard for RPI CM4\n* [sodimm-ddr5-tester](https://github.com/antmicro/sodimm-ddr5-tester)\n  * Antmicro ddr5 tester board\n\n# Education\n\n## Analog Design\n\n* [book-on-mos-stagse](https://github.com/bmurmann/Book-on-MOS-stages)\n  * Analysis and Design of Elementary MOS Amplifier Stages\n* [SiliWiz](https://tinytapeout.com/siliwiz/introduction/)\n  * Browser based interactive circuit design tool.\n\n## Board Design\n\n## Digital Design\n\n* [cornell-ece4750](https://github.com/cornell-ece4750)\n  * ECE 4750 Computer Architecture\n* [cornell-ece5745](https://github.com/cornell-ece5745)\n  * ECE 5745 Complex Digital ASIC Design\n* [stanford-ee272a](https://priyanka-raina.github.io/ee272a-winter2021)\n  * EE272A Design Projects in VLSI Systems I\n* [stanford-ee272b](https://priyanka-raina.github.io/ee272b-spring2021)\n  * EE272B Design Projects in VLSI Systems II\n\n## FPGA Design\n\n----\n\n# Other Awesome Lists\n\n* [ben-marshall](https://github.com/ben-marshall/awesome-open-hardware-verification)\n  * Hardware verification\n* [computer-engineering-resources](https://github.com/rajesh-s/computer-engineering-resources)\n  * A curated list of Computer Engineering/Architecture resources\n* [delftopenhardware](https://github.com/delftopenhardware/awesome-open-hardware)\n  * Open hardware materials\n* [drom](https://github.com/drom/awesome-hdl)\n  * HDL languages\n* [hdl](https://github.com/hdl/awesome)\n  * Hardware description resources\n* [kicad-3rd-party-tools](https://github.com/devbisme/kicad-3rd-party-tools)\n  * List of 3rd party KiCad software packages\n* [mattvenn](https://github.com/mattvenn/awesome-opensource-asic-resources)\n  * ASIC resources\n* [pkuzjx](https://github.com/pkuzjx/eda-collection)\n  * Open source EDA resources\n* [semiconduoctor-startups](https://github.com/aolofsson/awesome-semiconductor-startups)\n  * Semiconductor startups\n* [joamateb](https://github.com/joamatab/awesome_photonics)\n  * Photonics\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faolofsson%2Fawesome-hardware-tools","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Faolofsson%2Fawesome-hardware-tools","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faolofsson%2Fawesome-hardware-tools/lists"}