{"id":29014815,"url":"https://github.com/armmbed/fpga-ci-test-shield","last_synced_at":"2026-02-03T00:05:57.691Z","repository":{"id":46828699,"uuid":"195458939","full_name":"ARMmbed/fpga-ci-test-shield","owner":"ARMmbed","description":"Verilog source code, tests and utilities for the FPGA CI Test Shield","archived":false,"fork":false,"pushed_at":"2021-09-23T08:20:42.000Z","size":2881,"stargazers_count":6,"open_issues_count":0,"forks_count":8,"subscribers_count":8,"default_branch":"master","last_synced_at":"2023-08-03T07:54:06.257Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ARMmbed.png","metadata":{"files":{"readme":"readme.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-07-05T19:35:21.000Z","updated_at":"2023-08-03T07:54:06.258Z","dependencies_parsed_at":"2022-09-23T05:20:52.103Z","dependency_job_id":null,"html_url":"https://github.com/ARMmbed/fpga-ci-test-shield","commit_stats":null,"previous_names":[],"tags_count":1,"template":null,"template_full_name":null,"purl":"pkg:github/ARMmbed/fpga-ci-test-shield","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ARMmbed%2Ffpga-ci-test-shield","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ARMmbed%2Ffpga-ci-test-shield/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ARMmbed%2Ffpga-ci-test-shield/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ARMmbed%2Ffpga-ci-test-shield/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ARMmbed","download_url":"https://codeload.github.com/ARMmbed/fpga-ci-test-shield/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ARMmbed%2Ffpga-ci-test-shield/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":261945427,"owners_count":23234246,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-06-25T20:14:17.225Z","updated_at":"2026-02-03T00:05:57.686Z","avatar_url":"https://github.com/ARMmbed.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# FPGA CI Test Shield\n\nThis project contains RTL and tests for the FPGA CI Test Shield. The FPGA CI Test Shield is a shield which can be attached to Mbed boards to allow in-depth testing of all connected pins.\n\n## Required software and hardware\n\nBuilding and testing this project require the following tools and hardware:\n - [Vivado HL WebPACK](https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html) for FPGA synthesis, implementation and programming\n - [iverilog](http://iverilog.icarus.com/) for simulation testing\n - [GTKWave](http://gtkwave.sourceforge.net/) for viewing simulation waveforms\n - FPGA CI Test Shield\n - Any Mbed enabled board\n\n## Simulation testing\n\nBatch files are provided to run simulation on various parts of the system. To run the tests, open a terminal in the `sim` directory and run the `build_and_run_*.bat` for the desired test. If an error occurs, it will be printed. Note - this also starts a waveform viewer at the end of the simulation.\n\n## Building and programming the FPGA image\n\nVivado is used to build FPGA images. The following sequence can be used to create a programmable image:\n - Generate and open the project\n    - Start Vivado\n    - Click \"Window -\u003e Tcl Console\"\n    - In the Tcl console, change the current directory to that of the project `\u003e cd \u003cproject location\u003e/fpga-ci-test-shield` (for those using Windows, Vivado uses forward slashes instead of backslashes for file paths)\n    - In the Tcl console, generate and open the project `\u003e source generate_project_shield.tcl`\n - Generate bitstream (.bit and .bin files) inside Vivado by clicking the `Generate Bitstream` button\n - Add a CRC to the new image\n    - Start command prompt in the project directory\n    - Run the post process script `\u003e python post_process_bitstream.py project_shield\\project_shield.runs\\impl_1\\mbed_tester_shield_top.bin mbed_tester_shield_top_crc.bin`\n - Program the bitstream file to the device using the update script and Mbed code found in the [fpga-ci-test-shield-updater](https://github.com/ARMmbed/fpga-ci-test-shield-updater) project.\n\n## Example greentea testcase using FPGA CI test shield\n\n```C++\nvoid spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel)\n{\n    printf(\"SPI test on mosi=%s (%i), miso=%s (%i), sclk=%s (%i), ssel=%s (%i)\\r\\n\",\n            pinmap_ff_default_pin_to_string(mosi), mosi,\n            pinmap_ff_default_pin_to_string(miso), miso,\n            pinmap_ff_default_pin_to_string(sclk), sclk,\n            pinmap_ff_default_pin_to_string(ssel), ssel);\n\n    // Remap pins for test\n    tester.reset();\n    tester.pin_map_set(mosi, MbedTester::LogicalPinSPIMosi);\n    tester.pin_map_set(miso, MbedTester::LogicalPinSPIMiso);\n    tester.pin_map_set(sclk, MbedTester::LogicalPinSPISclk);\n    tester.pin_map_set(ssel, MbedTester::LogicalPinSPISsel);\n\n    // Initialize mbed SPI pins\n    spi_t spi;\n    spi_init(\u0026spi, mosi, miso, sclk, ssel);\n    spi_format(\u0026spi, 8, 0, 0);\n    spi_frequency(\u0026spi, 1000000);\n\n    // Reset tester stats and select SPI\n    tester.peripherals_reset();\n    tester.select_peripheral(MbedTester::SPI);\n\n    // Send and receive test data\n    uint32_t checksum = 0;\n    for (int i = 0; i \u003c TRANSFER_COUNT; i++) {\n        uint8_t data = spi_master_write(\u0026spi, (0 - i) \u0026 0xFF);\n        TEST_ASSERT_EQUAL(i \u0026 0xFF, data);\n\n        checksum += (0 - i) \u0026 0xFF;\n    }\n\n    // Verify that the transfer was successful\n    TEST_ASSERT_EQUAL(TRANSFER_COUNT, tester.spi_transfer_count());\n    TEST_ASSERT_EQUAL(checksum, tester.spi_to_slave_checksum());\n\n    printf(\"  Pin combination works\\r\\n\");\n\n    spi_free(\u0026spi);\n    tester.reset();\n}\n```\n\n## License and contributions\n\nThe software is provided under the [Apache-2.0 license](https://github.com/ARMmbed/mbed-os/blob/master/LICENSE-apache-2.0.txt). Contributions to this project are accepted under the same license. Please see [contributing.md](https://github.com/ARMmbed/mbed-os/blob/master/CONTRIBUTING.md) for more information.\n\nThis project contains code from other projects. The original license text is included in those source files. They must comply with our [license guide](https://os.mbed.com/docs/mbed-os/latest/contributing/license.html).\n\nFolders containing files under different permissive license than Apache 2.0 are listed in the [LICENSE](https://github.com/ARMmbed/mbed-os/blob/master/LICENSE.md) file.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Farmmbed%2Ffpga-ci-test-shield","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Farmmbed%2Ffpga-ci-test-shield","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Farmmbed%2Ffpga-ci-test-shield/lists"}