{"id":20373400,"url":"https://github.com/arxiver/pipelined-mips","last_synced_at":"2026-03-05T21:13:04.720Z","repository":{"id":67315876,"uuid":"255062225","full_name":"arxiver/Pipelined-MIPS","owner":"arxiver","description":"MIPS Pipelined CPU simulation using VHDL language","archived":false,"fork":false,"pushed_at":"2020-05-30T02:38:56.000Z","size":1609,"stargazers_count":6,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-01T04:15:15.948Z","etag":null,"topics":["hardware-designs","processor","processor-architecture","processor-simulator","vhdl","vhdl-code"],"latest_commit_sha":null,"homepage":null,"language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/arxiver.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2020-04-12T10:52:39.000Z","updated_at":"2023-12-31T14:43:16.000Z","dependencies_parsed_at":"2023-12-31T18:25:07.021Z","dependency_job_id":"1dfeb2a4-dfc9-4607-b28d-5c42df1969dc","html_url":"https://github.com/arxiver/Pipelined-MIPS","commit_stats":null,"previous_names":["arxiver/pipelined-mips"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/arxiver%2FPipelined-MIPS","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/arxiver%2FPipelined-MIPS/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/arxiver%2FPipelined-MIPS/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/arxiver%2FPipelined-MIPS/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/arxiver","download_url":"https://codeload.github.com/arxiver/Pipelined-MIPS/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":241921824,"owners_count":20042763,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["hardware-designs","processor","processor-architecture","processor-simulator","vhdl","vhdl-code"],"created_at":"2024-11-15T01:18:10.816Z","updated_at":"2026-03-05T21:12:59.680Z","avatar_url":"https://github.com/arxiver.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Pipelined-MIPS\nMIPS Pipelined CPU simulation using VHDL language\n# DOCS\nhttps://docs.google.com/document/d/1d16zJOv1bv6DRT5dF5ue6NwOacjUEF2OJvH9ig1k5Uc/edit\nhttps://docs.google.com/spreadsheets/d/1Fy1Bc-1-45yjAi3iQWY8kK1qiGJYrgHOlyU1wzBdAVY/edit#gid=0\nhttps://www.lucidchart.com/documents/edit/317b22b2-413e-440e-9866-fd49fe1eb244/0_0?shared=true\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Farxiver%2Fpipelined-mips","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Farxiver%2Fpipelined-mips","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Farxiver%2Fpipelined-mips/lists"}