{"id":30340722,"url":"https://github.com/asiercl/logisim-pc","last_synced_at":"2026-02-10T23:01:47.360Z","repository":{"id":231590233,"uuid":"780495660","full_name":"AsierCL/Logisim-PC","owner":"AsierCL","description":"Very basic computer created in Logisim Evolution.","archived":false,"fork":false,"pushed_at":"2024-05-06T06:38:35.000Z","size":59,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2024-05-06T07:41:46.123Z","etag":null,"topics":["basic-computer","computer-architecture","digital-system-design","logisim-evolution"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/AsierCL.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-04-01T15:50:22.000Z","updated_at":"2024-05-06T06:38:38.000Z","dependencies_parsed_at":"2024-05-04T12:22:03.923Z","dependency_job_id":null,"html_url":"https://github.com/AsierCL/Logisim-PC","commit_stats":null,"previous_names":["asiercl/logisim-pc"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/AsierCL/Logisim-PC","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AsierCL%2FLogisim-PC","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AsierCL%2FLogisim-PC/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AsierCL%2FLogisim-PC/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AsierCL%2FLogisim-PC/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/AsierCL","download_url":"https://codeload.github.com/AsierCL/Logisim-PC/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AsierCL%2FLogisim-PC/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":270962679,"owners_count":24676027,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-08-18T02:00:08.743Z","response_time":89,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["basic-computer","computer-architecture","digital-system-design","logisim-evolution"],"created_at":"2025-08-18T08:19:18.372Z","updated_at":"2026-02-10T23:01:47.327Z","avatar_url":"https://github.com/AsierCL.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"\n# Computer in logisim\n\nThis is a very basic computer created in [Logisim Evolution](https://github.com/logisim-evolution/logisim-evolution). It only has simple functionalities implemented, which means it can work as a simple calculator with storage.\n![Implementation](Images/General.png)\n\n\n\n\n## Features\n\nThe computer is capable of performing ONLY ONE OPERATION PER CYCLE. These operations are divided into 4 groups:\n\n- In-memory data manipulation\n- Cached data manipulation\n- Saving the ALU result in memory\n- Arithmetic operations in the ALU\n\n\n\n\n## Usage\n\nThis computer has a simple operation, based on some simple basic rules. \n- The computer allows data to be directly loaded into memory banks and cache memory.\n- To operate with two numbers, they must be in the respective caches.\n- The only asynchronous element of the computer is the ALU.\n- The numbers are encoded with 8 bits in two’s complement. Therefore, the range of numbers is from -128 to 127.\n\n\n\n\n## Binary instruction encoding\n\nThe last 2 bits will always correspond to the operating mode.\n\n\n\n### In-memory data manipulation\n\nThis type of instruction allows you to modify some of the data stored in the memory banks. The available mods are shift and write.\n\nThis instruction is divided into 5 fields. From left to right: number to be loaded (in case of loading), action code, cell identifier, bank identifier and action code.\n\n- The number corresponds to the first 8 bits. This will only be significant in case of load. Otherwise, those positions can have any value.\n\n- The action code is encoded in 2 bits.\n    - 00 -\u003e Maintains the previous value.\n    - 01 -\u003e Shift right one position.\n    - 10 -\u003e Shift left one position.\n    - 11 -\u003e Load the value stored in the first 8 bits.\n\n- The cell number, encoded in 2 bits. There are 4 cells per bank, so these are coded in binary from the number 0 (00) to 3 (11).\n\n- The bank number, encoded in 2 bits. There are 4 records, and these are coded in the same way as the cells.\n\n- Action code. For in-memory data manipulation, the action code is always 00.\n\nExample: \n[00100001|11|10|01|00]\u003cbr\u003e\nLoading the number 33, in cell 2 of bank 1.\n\nExample: \n[xxxxxxxx|01|11|10|00]\u003cbr\u003e\nShift right the value found in cell 3 of record 2 one position to the right.\n\n\n### Cached data manipulation\n\nThis type of instruction allows you to modify the information in the registers. In turn, it contains two subtypes: Immediate or direct loading, and loading from memory. The ninth largest bit decides whether the instruction is of subtype 0 (immediate loading) or subtype 1 (loading from memory).\n\n\n#### Subtype 0 (Immediate loading)\n\nThis instruction subtype contains 6 fields, corresponding, from left to right, to the number being loaded, the operation subtype (0), two empty bits, the action code, the target register and the type code (01).\n\n- The number corresponds to the first 8 bits. This will only be significant in case of load. Otherwise, those positions can have any value.\n\n- The subtype is encoded with a bit, 0 in this case (immediate loading).\n\n- Two insignificant bits.\n\n- The action code is encoded in 2 bits.\n    - 00 -\u003e Maintains the previous value.\n    - 01 -\u003e Shift right one position.\n    - 10 -\u003e Shift left one position.\n    - 11 -\u003e Load the value stored in the first 8 bits.\n\n- The selection of register A or register B is encoded with one bit. This is 0 for the first case, and 1 for the second.\n\n- Action code. For cached data manipulation, the action code is always 01.\n\nExample:\n[00100001|0|xx|11|0|01]\u003cbr\u003e\nLoading number 33, in register A.\n\nExample: \n[xxxxxxxx|0|xx|10|1|01]\u003cbr\u003e\nShift left the value found in register B.\n\n\n#### Subtype 1 (Load from memory)\n\nThis instruction subtype contains 6 fields, corresponding, from left to right, 8 empty bits, the operation subtype (0), the cache to modify, the cell and the bank from which the number is obtained and the type code (01).\n\n- The first 8 bits are insignificant, because the number will be obtained from memory.\n\n- The subtype is encoded with a bit, 1 in this case (load from memory).\n\n- 1 bit to choose the caché to modify (0=A, 1=B)\n\n- The cell number, encoded in 2 bits. There are 4 cells per bank, so these are coded in binary from the number 0 (00) to 3 (11).\n\n- The bank number, encoded in 2 bits. There are 4 records, and these are coded in the same way as the cells.\n\n- Action code. For cached data manipulation, the action code is always 01.\n\nExample:\n[xxxxxxxx|1|0|10|11|01]\u003cbr\u003e\nLoad into cache A the number stored in cell 2 of bank 3.\n\n\n### Save ALU result in memory\n\nThis instruction allows the result obtained in the arithmetic logic unit (ALU) to be stored in memory. The fields of this instruction are 5: 8 empty bits, 2 bits of register action code (11), then 2 bits to choose the memory cell, and another 2 bits to choose the bank. Finally, the code for this instruction (10).\n\n#### ||| This function will be implemented in the future |||\n\n\n### ALU Operation\n\nWith this instruction, we will operate with the values previously loaded in records A and B. This is the only asynchronous operation of the computer. It consists of 11 empty bits, 3 operation, and 2 bits of the Instruction Code (11).\n\n- 11 bits vacios\n\n- 3 bits operation\n  - 000 Transfer A\n  - 001 A++\n  - 010 A+B\n  - 011 A+B+1\n  - 100 A+(¬B) 1's Complement\n  - 101 A+(¬B)+1 2's Complement\n  - 110 A--\n  - 111 Transfer A\n\n\n## Parts of the computer\n\n### ALU\n\nThis ALU is made up of 1 bit cells.\n\n![1bitCell](Images/ALU_unitary_module.png)\n\nChaining 8 of these, we can assemble the 8bits ALU.\n\n![ALU](Images/ALU.png)\n\n\n### Register\n\nThe records are based on Flip-Flops type D the version with displacement, which is finally used, is composed of unit modules.\n\n![MemoryModuleCell](Images/MemoryModule.png)\n\nIf we connect these chain modules with each other, both towards the following cell and to the previous one, we manage to register 8Bits with displacement in both directions.\n\n![MemoryModule](Images/Memory.png)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fasiercl%2Flogisim-pc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fasiercl%2Flogisim-pc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fasiercl%2Flogisim-pc/lists"}