{"id":26660079,"url":"https://github.com/astrogeekdk/risc-v-basic-simd","last_synced_at":"2025-12-31T14:31:56.432Z","repository":{"id":279056269,"uuid":"937598613","full_name":"astrogeekdk/RISC-V-Basic-SIMD","owner":"astrogeekdk","description":"A basic implemention of 8 lane vector SIMD in RISC-V 5 Stage Pipeline, written in Chisel and Scala.","archived":false,"fork":false,"pushed_at":"2025-02-23T13:49:25.000Z","size":13,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-25T11:18:29.382Z","etag":null,"topics":["processor","processor-architecture","processor-design","processor-simulator","risc-v","risc-v-assembly","risc-v-emulator","simd","simd-parallelism"],"latest_commit_sha":null,"homepage":"","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/astrogeekdk.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2025-02-23T13:11:03.000Z","updated_at":"2025-02-23T13:49:28.000Z","dependencies_parsed_at":null,"dependency_job_id":"8deb3cd6-b87c-49ce-b323-42b85227abf6","html_url":"https://github.com/astrogeekdk/RISC-V-Basic-SIMD","commit_stats":null,"previous_names":["astrophy-geek/risc-v-basic-simd","astrogeekdk/risc-v-basic-simd"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/astrogeekdk/RISC-V-Basic-SIMD","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/astrogeekdk%2FRISC-V-Basic-SIMD","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/astrogeekdk%2FRISC-V-Basic-SIMD/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/astrogeekdk%2FRISC-V-Basic-SIMD/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/astrogeekdk%2FRISC-V-Basic-SIMD/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/astrogeekdk","download_url":"https://codeload.github.com/astrogeekdk/RISC-V-Basic-SIMD/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/astrogeekdk%2FRISC-V-Basic-SIMD/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":265837676,"owners_count":23836558,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["processor","processor-architecture","processor-design","processor-simulator","risc-v","risc-v-assembly","risc-v-emulator","simd","simd-parallelism"],"created_at":"2025-03-25T11:18:30.904Z","updated_at":"2025-12-31T14:31:56.400Z","avatar_url":"https://github.com/astrogeekdk.png","language":"Scala","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISC-V Basic SIMD\n\n## Overview\n\nThis project implements a basic SIMD vector processor based on the RISC-V 5-stage pipeline architecture built in Scala and Chisel. Built it as a project in Computer Organisation course. It demonstrates the concept of vector processing with a fixed-length vector array (8 lanes). \nI implemented custom instructions `vload`, `vstore`, and `vadd` for simplicity. \n\n### Key Features:\n- **SIMD (Single Instruction, Multiple Data) processing**: Supports vectorized operations on 8-lane vectors (More of hard coded but serves the purpose.)\n- **RISC-V Pipeline**: The processor follows the classic 5-stage pipeline architecture.\n- **Custom Instructions**: Implements custom SIMD instructions (`vload`, `vstore`, `vadd`).\n- **Written in Chisel**: The hardware description is written in Chisel and tested with Scala-based testbenches.\n\n## Project Structure\n\n\n```\nRISC-V Basic SIMD/\n├── build.sbt                     # SBT build configuration\n├── src/                          # Source files\n│   ├── main/\n|   |──────── resources/\n|   |           ├── data.hex                        # Data Memory\n|   |           ├── inst.hex                        # Instruction Memory\n│   │──────── scala\n|   |           ├── ALU.scala                       # Arithmetic Logic Unit\n|   |           ├── DataMemory.scala                # Data memory model\n|   |           ├── DebugModule.scala               # Debugging utilities\n|   |           ├── InstructionMemoryLoader.scala   # Instruction memory loader\n|   |           ├── Processor.scala                 # Main Processor implementation\n│   └── test/\n│       ├── ProcessorTestor.scala   # Testbench for processor\n├── custom_assembler.py             # Python-based custom assembler for SIMD instructions\n|── # some sample assemblies to test\n└── README.md\n```\n\n- **src/main**: Contains the Chisel hardware description files, including the main processor, ALU, memory modules, and loader.\n- **src/test**: Contains Scala-based testbenches for verifying the design.\n- **custom_assembler.py**: A Python script that assembles custom instructions like `vload`, `vstore`, and `vadd` into machine code.\n- **samples**: Some basic sample assembly code I wrote to test the processor.\n\n## Installation\n\n### Prerequisites\n\n\n- **Java Development Kit (JDK)**: I don't remember the exact version \n- **Scala**: Ensure Scala is installed.\n- **SBT**: Build tool for Scala projects.\n- **Chisel**: Hardware construction language\n- **Python**: Required for running the custom assembler.\n\n### Setup Instructions\n\n1. **Clone the Repository**:\n\n   ```bash\n   git clone https://github.com/astrophy-geek/RISC-V-Basic-SIMD.git\n   cd RISC-V-Basic-SIMD\n   ```\n\n2. **Import into IntelliJ (Or use any editor)**:\n   - Open IntelliJ IDEA.\n   - Import the project as an Scala project.\n   - Make sure the project is correctly configured for Scala and Chisel.\n\n3. **Build the Project**:\n   - Use the following command to compile the project:\n\n     ```bash\n     sbt compile\n     ```\n\n4. **Run Tests**:\n   - To run tests (e.g., `ProcessorTestor`), use:\n\n     ```bash\n     sbt test\n     ```\n\n5. **Custom Assembler**:\n   - Generate custom assemblies using the script custom_assembler.py\n\n     ```bash\n     python assembler.py \u003cassembly_file\u003e [-o \u003coutput_file\u003e]\n     ```\n\n## Usage\n\nThe processor supports a basic vector array of 8 lanes and demonstrates SIMD operations using custom instructions. Here's an example workflow to run the demonstration:\n\n1. **Write Assembly Code**: Create a `.s` file (e.g., `test.s`). Example:\n\n   ```asm\n    addi x1, x0, 0\n    addi x2, x0, 32\n    addi x3, x0, 64\n    nop\n    vload v1, 0(x1)\n    vload v2, 0(x2)\n    nop\n    nop\n    nop\n    vadd v3, v1, v2\n    nop\n    nop\n    nop\n    vstore v3, 0(x3)\n   ```\n   I would surely like to implement forwarding to eliminate nops lol.\n\n2. **Assemble the Code**: Use the custom Python assembler to generate the binary file:\n\n     ```bash\n     python assembler.py \u003cassembly_file\u003e [-o \u003coutput_file\u003e]\n     ```\n\n3. **Run the Processor**: The processor will execute the instructions and perform the SIMD operations.\n\n4. **View Results**: Check the test output in the terminal.\n\n## Example Demonstration\n\nSimple Vector Addition\n\n### Input Vectors:\n```\nVector A = [1, 2, 3, 4, 5, 6, 7, 8]\nVector B = [8, 7, 6, 5, 4, 3, 2, 1]\n```\n\n### SIMD Operation:\n- Perform the `vadd` operation on the corresponding elements of the vectors.\n\n### Expected Output:\n```\nResult = [9, 9, 9, 9, 9, 9, 9, 9]\n```\n\n## Contributing\n\nDo whatever you like! Maybe tag/mention me!\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fastrogeekdk%2Frisc-v-basic-simd","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fastrogeekdk%2Frisc-v-basic-simd","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fastrogeekdk%2Frisc-v-basic-simd/lists"}