{"id":18404529,"url":"https://github.com/avakar/better_verilog","last_synced_at":"2025-04-12T19:57:44.592Z","repository":{"id":57414791,"uuid":"48182392","full_name":"avakar/better_verilog","owner":"avakar","description":null,"archived":false,"fork":false,"pushed_at":"2016-01-10T21:12:10.000Z","size":25,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-04-12T19:57:41.903Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/avakar.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2015-12-17T15:30:05.000Z","updated_at":"2022-04-20T20:45:51.000Z","dependencies_parsed_at":"2022-08-30T06:51:44.119Z","dependency_job_id":null,"html_url":"https://github.com/avakar/better_verilog","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/avakar%2Fbetter_verilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/avakar%2Fbetter_verilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/avakar%2Fbetter_verilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/avakar%2Fbetter_verilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/avakar","download_url":"https://codeload.github.com/avakar/better_verilog/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248625510,"owners_count":21135513,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-06T02:53:10.531Z","updated_at":"2025-04-12T19:57:44.568Z","avatar_url":"https://github.com/avakar.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"[![Build Status](https://travis-ci.org/avakar/better_verilog.svg?branch=master)](https://travis-ci.org/avakar/better_verilog)\n\nA succint, yet expressive HDL.\n\nGetting started\n===============\n\nInstall the project using pip:\n\n    $ pip install better_verilog\n\nOpen your favorite editor and create a new file called hello_world.bv.\nType the following.\n\n    module hello:\n        i clk\n        o led\n\n    def hello:\n        on posedge clk:\n            led \u003c= not led\n\nRun the translator:\n\n    $ bv hello_world.bv \u003e hello_world.v\n    $ cat hello_world.v\n    module hello(\n        input clk,\n        output reg led\n        );\n\n    always @(posedge clk) begin\n        led \u003c= !led;\n    end\n\n    endmodule\n\nSynthetize or simulate hello_world.v.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Favakar%2Fbetter_verilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Favakar%2Fbetter_verilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Favakar%2Fbetter_verilog/lists"}