{"id":13649355,"url":"https://github.com/avakar/usbcorev","last_synced_at":"2026-01-23T11:44:30.225Z","repository":{"id":8404604,"uuid":"9987004","full_name":"avakar/usbcorev","owner":"avakar","description":"A full-speed device-side USB peripheral core written in Verilog.","archived":false,"fork":false,"pushed_at":"2022-10-30T23:31:47.000Z","size":15,"stargazers_count":230,"open_issues_count":2,"forks_count":43,"subscribers_count":18,"default_branch":"master","last_synced_at":"2025-04-12T19:57:43.211Z","etag":null,"topics":["fpga","usb","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/avakar.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2013-05-10T17:56:09.000Z","updated_at":"2025-04-09T19:25:42.000Z","dependencies_parsed_at":"2023-01-11T17:23:10.371Z","dependency_job_id":null,"html_url":"https://github.com/avakar/usbcorev","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/avakar%2Fusbcorev","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/avakar%2Fusbcorev/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/avakar%2Fusbcorev/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/avakar%2Fusbcorev/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/avakar","download_url":"https://codeload.github.com/avakar/usbcorev/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248625510,"owners_count":21135513,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","usb","verilog"],"created_at":"2024-08-02T01:04:57.825Z","updated_at":"2026-01-23T11:44:30.193Z","avatar_url":"https://github.com/avakar.png","language":"Verilog","funding_links":[],"categories":["Verilog","硬件_其他"],"sub_categories":["网络服务_其他"],"readme":"This core allows you to embed a full-speed (12Mbps) USB 2.0 device core into your FPGA design.\n\n## Clocks\n\nThe core requires a reasonably precise 48MHz clock. You'd better derive it from a crystal oscillator.\n\n## Physical interface\n\nSince USB uses a bit of a weird signaling on its half-duplex (almost-)differential line,\nyou'll, need to do a little bit of work to connect it to the core. The following five signals\nconnect to D+ and D- USB signals.\n\n * `input rx_j` -- the differential value on D+/D- lines\n * `input rx_se0` -- single-ended zero detected: should be set when both D+ and D- lines are zero\n\n * `output tx_se0` -- transmit zeros on both USB lines; has priority over `tx_j`\n * `output tx_j` -- transmit `tx_j` to D+ and `~tx_j` to D-\n * `output tx_en` -- enable the trasmitter\n\nIf your FPGA doesn't have a differential receiver, then you can simply use two pins and connect them as follows.\nHowever, without a differential receiver, you will be outside of the USB specs.\nMake sure the inputs are synchronized to the USB clock.\n\n    inout usb_dp;\n    inout usb_dn;\n\n    // ...\n\n    wire usb_tx_se0, usb_tx_j, usb_tx_en;\n    usb usb0(\n        .rx_j(usb_dp),\n        .rx_se0(!usb_dp \u0026\u0026 !usb_dn),\n\n        .tx_se0(usb_tx_se0),\n        .tx_j(usb_tx_j),\n        .tx_en(usb_tx_en));\n\n    assign usb_dp = usb_tx_en? (usb_tx_se0? 1'b0: usb_tx_j): 1'bz;\n    assign usb_dn = usb_tx_en? (usb_tx_se0? 1'b0: !usb_tx_j): 1'bz;\n\nHowever, if you have a differential receiver, you'd better use it. Configuring this is FPGA-specific.\nFor Xilinx Spartan 6 family, I use four physical pins as follows.\n\n    // These pins are configured as differential inputs. Unfortunately,\n    // you can't use single-ended receivers nor transmitters on these pins.\n    input usb_sp;\n    input usb_sn;\n\n    // These pins are single-ended inouts.\n    inout usb_dp;\n    inout usb_dn'\n\n    // ...\n\n    IBUFDS usb_j_buf(.I(usb_sp), .IB(usb_sn), .O(usb_rx_j_presync));\n    synch usb_j_synch(clk_48, usb_rx_j_presync, usb_rx_j);\n    synch usb_se0_synch(clk_48, !usb_dp \u0026\u0026 !usb_dn, usb_rx_se0);\n\n    wire usb_tx_se0, usb_tx_j, usb_tx_en;\n    usb usb0(\n        .rx_j(usb_rx_j),\n        .rx_se0(usb_rx_se0),\n\n        .tx_se0(usb_tx_se0),\n        .tx_j(usb_tx_j),\n        .tx_en(usb_tx_en));\n\n    assign usb_dp = usb_tx_en? (usb_tx_se0? 1'b0: usb_tx_j): 1'bz;\n    assign usb_dn = usb_tx_en? (usb_tx_se0? 1'b0: !usb_tx_j): 1'bz;\n\nNote the synchronization after the receiver.\n\nWhichever pins you transmit on need to have resistors after them.\nThe exact values will depend on the internal resistance of the pins;\nusually something around 27 ohms will be ok.\n\nYou also need to pull the D+ line up to 3.3V via a 1.5k resistor.\nYou can pull it directly, or via a pin on your FPGA, if you want to\ndynamically attach/detach to the bus.\nMake sure to never pull the line down, the only valid outputs\nof the pullup pin are `1'b1` and `1'bz`.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Favakar%2Fusbcorev","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Favakar%2Fusbcorev","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Favakar%2Fusbcorev/lists"}