{"id":18077436,"url":"https://github.com/b00rg/32-bit-processor","last_synced_at":"2026-02-22T22:31:53.315Z","repository":{"id":259950658,"uuid":"856818909","full_name":"b00rg/32-bit-processor","owner":"b00rg","description":"Simulating a 32-bit processor using VHDL","archived":false,"fork":false,"pushed_at":"2025-03-30T19:14:57.000Z","size":10965,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-10-29T23:45:15.173Z","etag":null,"topics":["32-bit-processor","computer-architecture","processor","vhdl","vivado"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/b00rg.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2024-09-13T09:08:49.000Z","updated_at":"2025-03-30T19:15:01.000Z","dependencies_parsed_at":"2025-03-30T20:31:20.376Z","dependency_job_id":null,"html_url":"https://github.com/b00rg/32-bit-processor","commit_stats":null,"previous_names":["b00rg/32-bit-processor"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/b00rg/32-bit-processor","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/b00rg%2F32-bit-processor","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/b00rg%2F32-bit-processor/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/b00rg%2F32-bit-processor/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/b00rg%2F32-bit-processor/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/b00rg","download_url":"https://codeload.github.com/b00rg/32-bit-processor/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/b00rg%2F32-bit-processor/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29730138,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-22T20:09:16.275Z","status":"ssl_error","status_checked_at":"2026-02-22T20:09:13.750Z","response_time":110,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["32-bit-processor","computer-architecture","processor","vhdl","vivado"],"created_at":"2024-10-31T11:24:56.941Z","updated_at":"2026-02-22T22:31:53.292Z","avatar_url":"https://github.com/b00rg.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# 32-bit-processor\nThis project simulates a 32-bit processor using VHDL, implemented at the gate level. The goal is to provide a comprehensive simulation environment for understanding and testing a 32-bit processor's functionality.\n\n### Repository Contents:\n1. VHDL Simulation Code: The main VHDL code for simulating the processor (FILENAME.vhd).\n2. Testbench Code: VHDL code used to validate the processor's functionality (FILENAME_TB.vhd).\n\n3. Test Documentation: Detailed documentation outlining how the testbench was structured and executed (FILENAME_DOC.pdf).\n\n4. Generated Schematic: The schematic of the processor generated using Vivado (FILENAME_Schematic.pdf).\n\n5. Simulation Waveform: A waveform generated from the testbench, labeled with various test cases (FILENAME_TD0X.png).\n\n6. Propagation Delay Information: A detailed waveform showing the propagation delay from the simulation (FILENAME_TD0X.png).\n\n### Project Structure\nThe project is organized into four primary folders, each containing the components necessary for simulating specific parts of the processor:\n1. Register File: Contains components required to simulate the Register File (Register_File/RF_FILENAME).\n2. Functional Unit: Includes components necessary for simulating the Functional Unit (Functional_Unit/DP_FILENAME).\n3. Datapath: Contains the components that combine the Register File and Functional Unit to simulate the full Datapath (Datapath/DP_FILENAME).\n4. Processor: Integrates the Datapath, Register File, and Functional Unit to simulate the complete 32-bit processor (Processor/CPU_FILENAME).\n\n---\n\nThe schematic of the final processor is as follows:\n\n![32-bit-processor-diagram](https://github.com/user-attachments/assets/e3cb8e46-d9f1-41f0-bfda-30bf2fb6eb07)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fb00rg%2F32-bit-processor","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fb00rg%2F32-bit-processor","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fb00rg%2F32-bit-processor/lists"}