{"id":22624623,"url":"https://github.com/barrettotte/subarashii-cpu","last_synced_at":"2025-04-11T03:06:58.706Z","repository":{"id":114091405,"uuid":"170013753","full_name":"barrettotte/Subarashii-CPU","owner":"barrettotte","description":"A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.","archived":false,"fork":false,"pushed_at":"2020-08-03T21:23:51.000Z","size":11022,"stargazers_count":8,"open_issues_count":0,"forks_count":1,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-03-25T00:51:12.566Z","etag":null,"topics":["cpu","homebrew","risc-processor","verilog","verilog-cpu"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/barrettotte.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-02-10T18:53:41.000Z","updated_at":"2024-07-18T00:44:35.000Z","dependencies_parsed_at":"2023-06-12T14:00:28.786Z","dependency_job_id":null,"html_url":"https://github.com/barrettotte/Subarashii-CPU","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/barrettotte%2FSubarashii-CPU","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/barrettotte%2FSubarashii-CPU/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/barrettotte%2FSubarashii-CPU/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/barrettotte%2FSubarashii-CPU/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/barrettotte","download_url":"https://codeload.github.com/barrettotte/Subarashii-CPU/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248333602,"owners_count":21086200,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","homebrew","risc-processor","verilog","verilog-cpu"],"created_at":"2024-12-09T00:17:04.997Z","updated_at":"2025-04-11T03:06:58.682Z","avatar_url":"https://github.com/barrettotte.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Subarashii-CPU\n\nA 16-bit RISC CPU inspired by MIPS. \nI designed this to learn more about computer architecture/organization.\n\n\n## Specifications\n* 16-bit RISC\n* Harvard architecture\n* single cycle execution\n* 16 x 16-bit registers\n* 64KB ROM with 16-bit instructions\n* 64KB RAM with memory mapped I/O\n\n\n\n## Physical Implementation\n* Simple bill of materials located at [https://github.com/barrettotte/Subarashii-CPU/docs/bom.xlsx](docs/bom.xlsx)\n* More documentation to come such as schematics and screenshots\n\n\n\n## Instruction Set\n| Opcode | Syntax                | Logic                  | Description                                             |\n| ------ | --------------------- | ---------------------- | ------------------------------------------------------- |\n| 0000   | ```ADD R1,R2,R3```    | R1 = R2 + R3           | register addition                                       |\n| 0001   | ```SUB R1,R2,R3```    | R1 = R2 - R3           | register subtraction                                    |\n| 0010   | ```AND R1,R2,R3```    | R1 = R2 \u0026 R3           | logical AND                                             |\n| 0011   | ```ORR R1,R2,R3```    | R1 = R2 \\| R3          | logical OR                                              |\n| 0100   | ```NOT R1,R2,R0```    | R1 = ~R2               | logical NOT                                             |\n| 0101   | ```XOR R1,R2,R3```    | R1 = R2 ^ R3           | logical XOR                                             |\n| 0110   | ```LSR R1,R2,R0```    | R1 = R2 \u003e\u003e 1           | logical shift right                                     |\n| 0111   | ```LSL R1,R2,R0```    | R1 = R2 \u003c\u003c 1           | logical shift left                                      |\n| 1000   | ```ADI R1,00001111``` | R1 += 000001111        | Add immediate to R1                                     |\n| 1001   | ```SWP R1,R2,R3```    | R1 = R2[HI] R3[LO]     | Swap bytes of registers                                 |\n| 1010   | ```LDW R1,R2,R0```    | R1 = [R2]              | load word into R1 from memory address R2                |\n| 1011   | ```STW R0,R2,R1```    | [R2] = R1              | store word in R1 at memory address R2                   |\n| 1100   | ```BRZ R0,R1,R2```    | PC = R1-0=Z ? R2 : PC  | relative branch to R2 if result of R1-0 sets zero flag  |\n| 1101   | ```JAL R1,R2```       | R1 = PC+2 ; PC = R2    | jump to address R2 and link to R1                       |\n| 1110   | ``` ```               |                        |                                                         |\n| 1111   | ``` ```               |                        |                                                         |\n\n\nNote: I left two instructions open so I can add new features or any missing functionality; I'm sure I missed something.\n\n\n## Register Set\n* R0     - zero register\n* R1-R11 - general purpose\n* R12    - scratch register \n* R13    - status register (flags, control, errors)\n* R14    - link register\n* R15    - stack pointer\n\nFor now, I have not simulated these with Verilog. \nThese are most likely to change after experimenting more.\n\n\n## Status Flags\nThese flags are also very likely to change in the future.\n\n| Index | Flag | Description          |\n| ----- | ---- | -------------------- |\n| 0     | Z    | Zero                 |\n| 1     | C    | Carry                |\n| 2     | N    | Negative             |\n| 3     | V    | Overflow             |\n| 4     | U    | Reserved             |\n| 5     | E    | Exception            |\n| 6     | M    | CPU Mode             |\n| 7     | IE   | Interrupt Enable     |\n| 8     | I0   | Software Interrupt 1 |\n| 9     | I1   | Software Interrupt 2 |\n| 10    | I2   | Software Interrupt 3 |\n| 11    | I3   | Hardware Interrupt 1 |\n| 12    | I4   | Hardware Interrupt 2 |\n| 13    | I5   | Hardware Interrupt 3 |\n| 14    | I6   | Hardware Interrupt 4 | \n| 15    | I7   | Hardware Interrupt 5 |\n\n\n## Example Assembly / Machine Code\nI have not made an assembler yet, but it will probably look something like this.\nThe commented machine code is what is used in [https://github.com/barrettotte/Subarashii-CPU/src/rom.v](src/rom.v) to run instructions.\n\nThis example is located in [https://github.com/barrettotte/Subarashii-CPU/test/tests.asm](test/tests.asm).\n```assembly\n; Test cases - Machine code used in src/rom.v\n;\n;\n; Test ALU\nADD R0,R0,R0     ; [000] = 0000000000000000\nADI R1,0x02      ; [002] = 1000000100000010\nADI R2,0x01      ; [004] = 1000001000000001\nADD R3,R2,R1     ; [006] = 0000001100100001\nSUB R3,R3,R0     ; [008] = 0001001100110000\nAND R2,R2,R3     ; [010] = 0010001000100011\nORR R2,R3,R2     ; [012] = 0011001000110010\nNOT R4,R4,R0     ; [014] = 0100010001000000\nXOR R4,R4,R4     ; [016] = 0101010001000100\nLSR R2,R2,R0     ; [018] = 0110001000100000\nLSL R2,R2,R0     ; [020] = 0111001000100000\nXOR R1,R1,R1     ; [022] = 0101000100010001\nXOR R2,R2,R2     ; [024] = 0101001000100010\nXOR R3,R3,R3     ; [026] = 0101001100110011\nXOR R4,R4,R4     ; [028] = 0101010001000100\n;\n; Test SWP\nADI R1,11001100  ; [030] = 1000000111001100\nADI R2,10101010  ; [032] = 1000001010101010\nSWP R3,R1,R2     ; [034] = 1001001100010010\nXOR R1,R1,R1     ; [036] = 0101000100010001\nXOR R2,R2,R2     ; [038] = 0101001000100010\nXOR R3,R3,R3     ; [040] = 0101001100110011\n;\n; Test Memory\nADI R1,0x02      ; [042] = 1000000100000010  (value)\nADI R2,0x08      ; [044] = 1000001000001000  (address)\nSTW R0,R2,R1     ; [046] = 1011000000100001  (store R1 at address R2)\nXOR R1,R1,R1     ; [048] = 0101000100010001\nLDW R1,R2,R0     ; [050] = 1010000100100000  (load R1 from address R2)\nADD R0,R1,R0     ; [052] = 0000000000010000\nXOR R1,R1,R1     ; [054] = 0101000100010001\nXOR R2,R2,R2     ; [056] = 0101001000100010\n;\n; Test Branch (relative addressing)\nADI R1,0x03      ; [058] = 1000000100000011  (skip next 3 instructions if Z)\nBRZ R0,R0,R1     ; [060] = 1100000000000001  (0 - 0 == 0)\nADD R0,R0,R0     ; [062] = 0000000000000000  (will be skipped)\nADD R0,R0,R0     ; [064] = 0000000000000000  (will be skipped)\nADD R0,R0,R0     ; [066] = 0000000000000000  (will be skipped)\nADI R1,0x07      ; [068] = 1000000100000111  (branch lands here)\nXOR R1,R1,R1     ; [070] = 0101000100010001\n;\n; Test Jump (absolute addressing)\nADI R1,0x52      ; [072] = 1000001001010010  (address 082)\nJAL R1,R2,R0     ; [074] = 1101000100100000  (link to R1, jump to R2)\nADD R0,R0,R0     ; [076] = 0000000000000000  (will be skipped)\nADD R0,R0,R0     ; [078] = 0000000000000000  (will be skipped)\nADD R0,R0,R0     ; [080] = 0000000000000000  (will be skipped)\nADD R1,R1,R0     ; [082] = 0000000100010000  (jump lands here)\nXOR R1,R1,R1     ; [084] = 0101000100010001\nXOR R2,R2,R2     ; [086] = 0101001000100010\n;\n```\n\n\n## Future Goals\n* Assembler\n  * probably in C, Python, or Rust\n  * pseudo opcodes for missing opcodes like ```PSH```, ```POP```, ```MOV```, ```JMP```, etc.\n* Video card interface\n* Serial interface\n* Keyboard interface\n* Very very basic operating system\n* Basic programming language with compiler targeted for this CPU\n\n\n## References\n* [Icarus Verilog](http://iverilog.icarus.com/)\n* [GTKwave](http://gtkwave.sourceforge.net/)\n* [Digital Computer Electronics](https://www.amazon.com/Digital-Computer-Electronics-Albert-Malvino/dp/0028005945)\n* [Essentials of Computer Organization and Architecture](https://www.amazon.com/Essentials-Computer-Organization-Architecture-Linda/dp/1284123030)\n* [Elements of Computing Systems](https://www.amazon.com/Elements-Computing-Systems-Building-Principles/dp/0262640686)\n* [Nand2Tetris Course](https://www.nand2tetris.org/)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbarrettotte%2Fsubarashii-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbarrettotte%2Fsubarashii-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbarrettotte%2Fsubarashii-cpu/lists"}