{"id":22624586,"url":"https://github.com/barrettotte/thoth-rv32","last_synced_at":"2026-02-08T18:04:14.205Z","repository":{"id":258737187,"uuid":"871773353","full_name":"barrettotte/thoth-rv32","owner":"barrettotte","description":"Single cycle RISC-V core supporting most of RV32I","archived":false,"fork":false,"pushed_at":"2024-10-17T23:52:18.000Z","size":20,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-02-03T13:13:12.623Z","etag":null,"topics":["basys3","rv32i"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/barrettotte.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-10-12T22:28:04.000Z","updated_at":"2024-10-17T23:57:48.000Z","dependencies_parsed_at":null,"dependency_job_id":"326555b9-9cdf-4a36-a96d-d162064c5a0e","html_url":"https://github.com/barrettotte/thoth-rv32","commit_stats":null,"previous_names":["barrettotte/thoth-rv32"],"tags_count":0,"template":false,"template_full_name":"barrettotte/fpga-dev-vscode","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/barrettotte%2Fthoth-rv32","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/barrettotte%2Fthoth-rv32/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/barrettotte%2Fthoth-rv32/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/barrettotte%2Fthoth-rv32/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/barrettotte","download_url":"https://codeload.github.com/barrettotte/thoth-rv32/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246131335,"owners_count":20728303,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["basys3","rv32i"],"created_at":"2024-12-09T00:16:49.719Z","updated_at":"2026-02-08T18:04:14.134Z","avatar_url":"https://github.com/barrettotte.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# thoth-rv32\n\nSingle cycle RISC-V core supporting most of RV32I.\n\nImplemented RV32I instructions minus `FENCE`, `ECALL`, `EBREAK`, and `CSRR`.\n\n## Limitations\n\n- I did not implement entire RV32I instruction set\n- Memory is small and does not synthesize to BRAM of FPGA\n- This is only partially tested since this was meant as a warmup project (and I'm lazy)\n  - everyone seems to recommend testing with - https://github.com/riscv-software-src/riscv-tests\n- I'm not sure if I'll convert this to a pipelined design or save it for another project\n\n## Development\n\nRequirements:\n- Vivado 2024.1+ (installed in Windows, not WSL)\n- WSL\n- GTKWave (in WSL `apt-get install gtkwave -y`)\n- Icarus Verilog (in WSL `apt-get install iverilog -y`)\n\nVerify Vivado is installed on Windows and its binaries (`xilinx/Vivado/2024.1/bin`) \nare in system path with `vivado -version`.\n\n### Workflow\n\n```sh\n# simulate module with Icarus Verilog\n./task.ps1 iverilog top\n\n# open waveform\n./task.ps1 gtkwave top\n\n# simulate specific module's testbench and generate waveform\n./task.ps1 vivado-sim top\n\n# build bitstream file\n./task.ps1 vivado-build\n\n# build and upload bitstream to FPGA\n./task.ps1 vivado-upload\n```\n\n## References\n\n- [Basys 3 Reference Manual](https://digilent.com/reference/programmable-logic/basys-3/reference-manual)\n- [Vivado Design Suite Tcl Command Reference Guide](https://docs.amd.com/r/en-US/ug835-vivado-tcl-commands)\n- https://projectf.io/posts/vivado-tcl-build-script/\n- https://github.com/riscv/riscv-isa-manual/releases/tag/20240411\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbarrettotte%2Fthoth-rv32","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbarrettotte%2Fthoth-rv32","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbarrettotte%2Fthoth-rv32/lists"}