{"id":49568479,"url":"https://github.com/bbangjee/cse3016_computer_science_lab","last_synced_at":"2026-05-03T12:47:20.866Z","repository":{"id":303529886,"uuid":"1015784289","full_name":"bbangjee/cse3016_computer_science_lab","owner":"bbangjee","description":"2024-2 컴퓨터공학실험II","archived":false,"fork":false,"pushed_at":"2025-07-08T03:46:26.000Z","size":8200,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-05-03T12:47:16.394Z","etag":null,"topics":["digital-logic","fpga","university-project","verilog","vivado"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/bbangjee.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2025-07-08T03:23:42.000Z","updated_at":"2026-01-03T14:42:04.000Z","dependencies_parsed_at":"2025-07-08T06:08:10.524Z","dependency_job_id":"7348a669-4806-4534-844f-8e93b3b82c31","html_url":"https://github.com/bbangjee/cse3016_computer_science_lab","commit_stats":null,"previous_names":["bbangjee/cse3016_computer_science_lab"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/bbangjee/cse3016_computer_science_lab","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bbangjee%2Fcse3016_computer_science_lab","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bbangjee%2Fcse3016_computer_science_lab/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bbangjee%2Fcse3016_computer_science_lab/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bbangjee%2Fcse3016_computer_science_lab/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/bbangjee","download_url":"https://codeload.github.com/bbangjee/cse3016_computer_science_lab/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bbangjee%2Fcse3016_computer_science_lab/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":32569714,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-03T06:36:36.687Z","status":"ssl_error","status_checked_at":"2026-05-03T06:36:09.306Z","response_time":103,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["digital-logic","fpga","university-project","verilog","vivado"],"created_at":"2026-05-03T12:47:19.593Z","updated_at":"2026-05-03T12:47:20.859Z","avatar_url":"https://github.com/bbangjee.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# CSE3016 Computer Science Lab 2\n서강대학교 컴퓨터공학과 컴퓨터공학실험2 과제 모음\n\n## 📚 Course Information\n- **Course Name**: CSE3016 Computer Science Lab 2 (컴퓨터공학실험2)\n- **University**: Sogang University (서강대학교)\n- **Department**: Computer Science \u0026 Engineering\n- **Semester**: 2024\n\n## 🛠️ Lab Topics\n각 주차별로 다음과 같은 내용들을 다룹니다:\n\n- **Week 01**: Vivado 기초\n- **Week 02**: Verilog 문법\n- **Week 03**: AND, OR, NOT gate\n- **Week 04**: NAND, NOR, XOR, AOI gate\n- **Week 05**: 드 모르간의 제1, 2 법칙과 Boolean 함수의 동작 확인 및 1 bit 비교기\n- **Week 06**: half adder, full adder, half subtractor, full subtractor, code converter\n- **Week 07**: parity checker(odd, even), parity generator(odd, even), two bit comparator(odd, even)\n- **Week 08**: segment display\n- **Week 09**: 2-to-4 decoder, 4-to-2 encoder, BCD-to-Decimal, 4-to-1 MUX, 1-to-4 deMUX, 4-to-16 decoder\n- **Week 10**: parallel adder, parallel subtractor, bcd adder\n- **Week 11**: d_ff, rs_ff_nand, rs_ff_nor\n- **Week 12**: 2 bit counter, 4bit decade counter, 4bit 2421 decade counter\n- **Week 13**: ring counter, shift register, updown counter\n- **Week 14**: moore machine, mealy machine\n\n## ⚠️ Notice\nWeek 03: Source files (xdc, testbench, design) are missing.\n\n보고서 관련 참고 사항: 13주차 예비보고서 (-1점), 8주차 결과보고서 (-2점), 2주차 결과보고서 (-3점)\n\n## 📋 Files Included\n각 주차 폴더에는 다음 파일들이 포함되어 있습니다:\n- `.xdc` files (제약 조건 파일)\n- Testbench files (시뮬레이션용)\n- Design files (설계 파일)\n- 실험 보고서 및 문서\n---","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbbangjee%2Fcse3016_computer_science_lab","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbbangjee%2Fcse3016_computer_science_lab","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbbangjee%2Fcse3016_computer_science_lab/lists"}