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The design is accompanied by a testbench for thorough functional verification.\n\n## Project Structure\n```\n.\n├── ADD_MUX.sv        # Address Mux module\n├── tb_ADD_MUX.sv     # Testbench for Address Mux\n└── README.md         # Project documentation\n```\n\n## Address Mux Module (`ADD_MUX.sv`)\n**Features:**\n- Selects between instruction address and operand address.\n- Default address width is 5 bits, customizable via parameter.\n\n**Parameters:**\n- `WIDTH_ADDRESS_BIT` (default: 5): Width of the address signals.\n\n**Ports:**\n- `instr_address` (`[WIDTH_ADDRESS_BIT-1:0]`): Instruction address input.\n- `operand_address` (`[WIDTH_ADDRESS_BIT-1:0]`): Operand address input.\n- `select` (`1-bit`): Control signal (0 selects `instr_address`, 1 selects `operand_address`).\n- `address_out` (`[WIDTH_ADDRESS_BIT-1:0]`): Selected address output.\n\n**Implementation:**\nThe mux uses a simple ternary operator:\n```systemverilog\nassign address_out = (select) ? operand_address : instr_address;\n```\n\n## Testbench (`tb_ADD_MUX.sv`)\nThe testbench verifies the Address Mux functionality with different input scenarios.\n\n**Test Vectors:**\n1. `select = 0`: Should choose `instr_address`.\n2. `select = 1`: Should choose `operand_address`.\n3. Change input values and repeat.\n\n**Simulation Output Example:**\n```\nTime = 0 | select = 0 | instr_address = 10101 | operand_address = 01010 | address_out = 10101\nTime = 10 | select = 1 | instr_address = 10101 | operand_address = 01010 | address_out = 01010\nTime = 20 | select = 0 | instr_address = 11100 | operand_address = 00011 | address_out = 11100\nTime = 30 | select = 1 | instr_address = 11100 | operand_address = 00011 | address_out = 00011\n```\n\n## How to Run\n1. Ensure you have Vivado or a SystemVerilog-compatible simulator installed.\n2. Open the project in your environment.\n3. Compile and simulate `tb_ADD_MUX.sv`.\n4. Observe the output and verify the behavior.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbeckversync%2Frisc_cpu_beckham","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbeckversync%2Frisc_cpu_beckham","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbeckversync%2Frisc_cpu_beckham/lists"}