{"id":21943651,"url":"https://github.com/ben-marshall/croyde-riscv","last_synced_at":"2026-01-05T05:04:08.162Z","repository":{"id":95888165,"uuid":"251418791","full_name":"ben-marshall/croyde-riscv","owner":"ben-marshall","description":"A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) 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Croyde RISC-V\n\n*A 3-stage, 64-bit RISC-V rv64imck micro-controller.*\n[![Build Status](https://www.travis-ci.com/ben-marshall/croyde-riscv.svg?branch=master)](https://www.travis-ci.com/ben-marshall/croyde-riscv)\n[![Documentation Status](https://readthedocs.org/projects/croyde-riscv/badge/?version=latest)](https://croyde-riscv.readthedocs.io/en/latest/?badge=latest)\n\n---\n\n- [Getting Started](#Getting-Started)\n- [Block Diagram](#Block-Diagram)\n- [Documentaton](docs/)\n- [FAQ](#FAQ)\n\n## Features \u0026 Block Diagram\n\nThis is a very simple 3-stage 64-bit micro-controller, implementing the\n`rv64imck` instruction set.\nIt comes as a *core* module, and a *core complex* (CCX), which wraps the\ncore with timers, boot ROM, some RAM and other small peripherals, with\na memory port to the outside world.\n\n![Block Diagram](docs/pipeline-diagram.png)\n\nNote that the [`K` extension](https://github.com/riscv/riscv-crypto)\nis for cryptography, and is still under development.\n\n## Getting Started\n\n- Required Dependencies:\n  [Yosys](http://www.clifford.at/yosys/documentation.html),\n  [Verilator](https://www.veripool.org/projects/verilator/wiki/Intro),\n  [Boolector](https://boolector.github.io/),\n  [Symbiyosys](https://symbiyosys.readthedocs.io/en/latest/)\n  and a\n  [RISC-V Toolchain](https://github.com/riscv/riscv-gnu-toolchain).\n\n- Checkout the repository:\n  ```sh\n   git checkout https://github.com/ben-marshall/croyde-riscv.git\n   cd croyde-riscv/\n   git submodule update --init --recursive\n  ```\n\n- Setup the project workspace:\n  ```sh\n  source bin/conf.sh\n  ```\n\n- [Synthesise the core](docs/flows-synthesis.md) using Yosys\n  [Yosys](http://www.clifford.at/yosys/documentation.html).\n\n- Verify the core using the \n  [riscv-formal](docs/flows-riscv-formal.md)\n  framework.\n\n- Run the RISC-V\n  [architectural compliance tests](docs/flows-arch-tests.md).\n\n- Run the [confidence tests](docs/flows-unit-tests.md) set.\n\n\n## FAQ\n\n- Can I use this for X? - Yes you can. It's all MIT licensed.\n\n- Should I use this for X? - Maybe. If you want a little RV64 core\n  for your project, that is free, go for it. However, see the next bullet\n  point.\n\n- Has this been verified? - I have high confidence the user level\n  ISA and instructions is correct though the riscv-formal framework.\n  Plus the basic RISC-V architectural tests all pass, which is a basic\n  tyre kick. I have less confidence in the priviliged architecture\n  and interrupts implementation, or the core complex. It works for me,\n  and my needs, but I've not done any exhaustive verification on it.\n\n- What's the point of a 64-bit *micro-controller*? - If it's good enough\n  for [SiFive](https://www.sifive.com/cores/s21) \n  it's good enough for me. I wanted to implement RV64 in the\n  simplest way possible to play around with on an cheap FPGA, which meant it\n  had to be small to fit! More seriously, if your key workloads involve\n  working on large variables, you might find a 64-bit core makes a lot\n  of sense.\n\n- What's in the name? - Nothing really. *Croyde* is a fantastic beach for\n  surfing near where I grew up and there wasn't much chance of someone\n  else picking the same name.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fben-marshall%2Fcroyde-riscv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fben-marshall%2Fcroyde-riscv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fben-marshall%2Fcroyde-riscv/lists"}