{"id":21943645,"url":"https://github.com/ben-marshall/verilog-probe","last_synced_at":"2026-03-04T20:03:37.378Z","repository":{"id":95888296,"uuid":"100417177","full_name":"ben-marshall/verilog-probe","owner":"ben-marshall","description":"A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.","archived":false,"fork":false,"pushed_at":"2017-09-12T19:10:35.000Z","size":208,"stargazers_count":11,"open_issues_count":1,"forks_count":3,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-04-22T19:11:28.265Z","etag":null,"topics":["debugger","fpga","hdl","probe","python3","uart","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ben-marshall.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2017-08-15T20:34:15.000Z","updated_at":"2025-04-12T02:56:38.000Z","dependencies_parsed_at":"2023-03-13T16:43:55.782Z","dependency_job_id":null,"html_url":"https://github.com/ben-marshall/verilog-probe","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/ben-marshall/verilog-probe","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-probe","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-probe/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-probe/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-probe/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ben-marshall","download_url":"https://codeload.github.com/ben-marshall/verilog-probe/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-probe/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30091579,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-04T19:41:02.502Z","status":"ssl_error","status_checked_at":"2026-03-04T19:40:05.550Z","response_time":59,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["debugger","fpga","hdl","probe","python3","uart","verilog"],"created_at":"2024-11-29T03:33:48.328Z","updated_at":"2026-03-04T20:03:37.359Z","avatar_url":"https://github.com/ben-marshall.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"\n# Verilog Probe\n\n[![Documentation Status](https://readthedocs.org/projects/verilog-probe/badge/?version=latest)](http://verilog-probe.readthedocs.io/README)\n\nA simple probe which takes commands \u0026 data over a simple interface and allows\nsoftware based control of an AXI bus and some general purpose registers.\n\n---\n\n## Implementation Details\n\nAll implementation stats are taken from the default Xilinx Vivado 2016.4\nbuild flow, targeting an Artix-7 FPGA at speed grade `-3`.\n\nStat                       | Value\n---------------------------|---------------------------------------------\n Flip-Flops                | 87  \n Latches                   | 0\n LUTs                      | 187\n Timing slack @ 100MHz     | 3.77ns\n\n![Cell Map](cells.png)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fben-marshall%2Fverilog-probe","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fben-marshall%2Fverilog-probe","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fben-marshall%2Fverilog-probe/lists"}