{"id":13775168,"url":"https://github.com/ben-marshall/verilog-vcd-parser","last_synced_at":"2025-04-22T19:10:36.850Z","repository":{"id":43351916,"uuid":"122072462","full_name":"ben-marshall/verilog-vcd-parser","owner":"ben-marshall","description":"A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.","archived":false,"fork":false,"pushed_at":"2022-03-06T16:11:12.000Z","size":78,"stargazers_count":91,"open_issues_count":6,"forks_count":36,"subscribers_count":5,"default_branch":"master","last_synced_at":"2025-03-29T18:01:58.521Z","etag":null,"topics":["parser","simulation","systemverilog","trace","vcd","verilog","vhdl"],"latest_commit_sha":null,"homepage":null,"language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ben-marshall.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2018-02-19T14:17:14.000Z","updated_at":"2024-12-25T04:24:33.000Z","dependencies_parsed_at":"2022-08-20T02:40:58.483Z","dependency_job_id":null,"html_url":"https://github.com/ben-marshall/verilog-vcd-parser","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-vcd-parser","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-vcd-parser/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-vcd-parser/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ben-marshall%2Fverilog-vcd-parser/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ben-marshall","download_url":"https://codeload.github.com/ben-marshall/verilog-vcd-parser/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250306638,"owners_count":21408926,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["parser","simulation","systemverilog","trace","vcd","verilog","vhdl"],"created_at":"2024-08-03T17:01:34.802Z","updated_at":"2025-04-22T19:10:36.829Z","avatar_url":"https://github.com/ben-marshall.png","language":"C++","funding_links":[],"categories":["Waveform Viewers"],"sub_categories":[],"readme":"\n# VCD Tools\nThis is a multipurpose utility for handling VCD files.  \nIt started as a fork of the excellent Verilog VCD Parser, therefore keeping its original README file below.  \n\n## Features\n* Display full path of signals contained within th VCD file.\n* Display the list of scopes within the VCD file.\n* Display VCD file header\n* Display number of toggles for each signal\n* Restrict VCD file to a range of timestamps\n\n## TODO\n* Export VCD file (useful for producing a cut-down VCD file)\n* Filter some signals/scopes (useful for the VCD export)\n\nPlease see below for the original Verilog VCD Parser README.md file:\n\n---\n# Verilog VCD Parser\n\n[![Documentation](https://codedocs.xyz/ben-marshall/verilog-vcd-parser.svg)](https://codedocs.xyz/ben-marshall/verilog-vcd-parser/)\n\nThis project implements a no-frills *Value Change Dump* (VCD) file parser, as\ndescribed in the IEEE System Verilog 1800-2012 standard. It can be used to\nwrite custom tools which need to read signal traces dumped out by Verilog (or\nVHDL) simulators.\n\n---\n\n## Getting Started\n\nAfter cloning the repository to your local machine, run the following in a\nshell:\n\n```sh\n$\u003e cd ./verilog-vcd-parser\n$\u003e make all\n```\n\nThis will build both the demonstration executable in `build/vcd-parser` and\nthe API documentation in `build/docs`.\n\n## Code Example\n\nThis code will load up a VCD file and print the hierarchy of the scopes\nand signals declared in it.\n\n```cpp\nVCDFileParser parser;\n\nVCDFile * trace = parser.parse_file(\"path-to-my-file.vcd\");\n\nif(trace == nullptr) {\n    // Something went wrong.\n} else {\n\n    for(VCDScope * scope : *trace -\u003e get_scopes()) {\n\n        std::cout \u003c\u003c \"Scope: \"  \u003c\u003c scope -\u003e  name  \u003c\u003c std::endl;\n\n        for(VCDSignal * signal : scope -\u003e signals) {\n\n            std::cout \u003c\u003c \"\\t\" \u003c\u003c signal -\u003e hash \u003c\u003c \"\\t\" \n                      \u003c\u003c signal -\u003e reference;\n\n            if(signal -\u003e size \u003e 1) {\n                std::cout \u003c\u003c \" [\" \u003c\u003c signal -\u003e size \u003c\u003c \":0]\";\n            }\n            \n            std::cout \u003c\u003c std::endl;\n\n        }\n    }\n\n}\n```\n\nWe can also query the value of a signal at a particular time. Because a VCD\nfile can have multiple signals in multiple scopes which represent the same\nphysical signal, we use the signal hash to access it's value at a particular\ntime:\n\n```cpp\n// Get the first signal we fancy.\nVCDSignal * mysignal = trace -\u003e get_scope(\"$root\") -\u003e signals[0];\n\n// Print the value of this signal at every time step.\n\nfor (VCDTime time : *trace -\u003e get_timestamps()) {\n\n    VCDValue * val = trace -\u003e get_signal_value_at( mysignal -\u003e hash, time);\n\n    std::cout \u003c\u003c \"t = \" \u003c\u003c time\n              \u003c\u003c \", \"   \u003c\u003c mysignal -\u003e reference\n              \u003c\u003c \" = \";\n    \n    // Assumes val is not nullptr!\n    switch(val -\u003e get_type()) {\n        case (VCD_SCALAR):\n            std::cout \u003c\u003c VCDValue::VCDBit2Char(val -\u003e get_value_bit());\n            break;\n        case (VCD_VECTOR):\n            VCDBitVector * vecval = val -\u003e get_value_vector()\n            for(auto it = vecval -\u003e begin();\n                     it != vecval -\u003e end();\n                     ++it) {\n                std::cout \u003c\u003c VCDValue::VCDBit2Char(*it);\n            }\n            break;\n        case (VCD_REAL):\n            std::cout \u003c\u003c val -\u003e get_value_real();\n        default:\n            break;\n    }\n\n    std::cout \u003c\u003c endl;\n\n}\n\n```\n\nThe example above is deliberately verbose to show how common variables and\nsignal attributes can be accessed.\n\n\n## Integration\n\nIt is assumed that given a set of source files, it will be easy for people to\nintegrate this as a submodule of their own projects. However, Flex and Bison\n*must* be run before all compilable source files are present. If integrating\nthis into a larger project, you will want to ensure the following commands are\nrun before compiling any of the VCD parser sources.\n\n```sh\n$\u003e make parser-srcs\n```\n\nThis will run flex and bison on the `.ypp` and `.l` files in `src/` and put\nthe generated parser and lexer code in `build/`. The complete file list for\ninclusion in a larger project is:\n\n```\nsrc/VCDFile.cpp\nsrc/VCDFileParser.cpp\nsrc/VCDValue.cpp\nbuild/VCDParser.cpp\nbuild/VCDScanner.cpp\n```\n\nWith header files located in both `src/` and `build/`.\n\n## Integration using static link library\n\n`build/libverilog-vcd-parser.a` and the required .hpp files are copied into `build/`.\n\nTo use these from another application add -I and the .a file to your gcc command line:\n\n```sh\n$ gcc -Ibuild/ build/libverilog-vcd-parser.a myapp.cpp\n```\n\n\n## Tools\n\n- The parser and lexical analyser are written using Bison and Flex\n  respectively.\n- The data structures and other functions are written using C++ 2011.\n- The build system is GNU Make.\n- The codebase is documented using Doxygen.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fben-marshall%2Fverilog-vcd-parser","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fben-marshall%2Fverilog-vcd-parser","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fben-marshall%2Fverilog-vcd-parser/lists"}