{"id":13775570,"url":"https://github.com/bensampson5/libsv","last_synced_at":"2025-05-11T07:32:54.588Z","repository":{"id":44582135,"uuid":"324010177","full_name":"bensampson5/libsv","owner":"bensampson5","description":"An open source, parameterized SystemVerilog digital hardware IP library","archived":false,"fork":false,"pushed_at":"2024-05-26T04:49:56.000Z","size":261,"stargazers_count":26,"open_issues_count":5,"forks_count":4,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-03-19T12:39:25.975Z","etag":null,"topics":["asic","asic-library","digital-design","fpga","fpga-library","hardware","hardware-designs","hardware-libraries","hdl","ip","systemverilog","verilog"],"latest_commit_sha":null,"homepage":"https://libsv.readthedocs.io/en/latest/","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/bensampson5.png","metadata":{"files":{"readme":"README.rst","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":"AUTHORS","dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-12-23T22:02:38.000Z","updated_at":"2025-02-18T07:11:37.000Z","dependencies_parsed_at":"2024-08-03T17:20:38.600Z","dependency_job_id":null,"html_url":"https://github.com/bensampson5/libsv","commit_stats":{"total_commits":80,"total_committers":1,"mean_commits":80.0,"dds":0.0,"last_synced_commit":"989a51a4be8c8089f2735557f5f7764005e49533"},"previous_names":[],"tags_count":2,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bensampson5%2Flibsv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bensampson5%2Flibsv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bensampson5%2Flibsv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bensampson5%2Flibsv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/bensampson5","download_url":"https://codeload.github.com/bensampson5/libsv/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253534084,"owners_count":21923515,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","asic-library","digital-design","fpga","fpga-library","hardware","hardware-designs","hardware-libraries","hdl","ip","systemverilog","verilog"],"created_at":"2024-08-03T17:01:41.606Z","updated_at":"2025-05-11T07:32:49.574Z","avatar_url":"https://github.com/bensampson5.png","language":"SystemVerilog","funding_links":[],"categories":["Libraries"],"sub_categories":[],"readme":".. image:: https://raw.githubusercontent.com/bensampson5/libsv/main/docs/source/_static/libsv_logo.svg\n   :align: center\n   :height: 150\n   :alt: LibSV\n\n------------------------------------------------------------------------------------------------------------------------\n\n.. image:: https://img.shields.io/pypi/v/libsv\n   :target: https://pypi.org/project/libsv/\n   :alt: PyPI\n\n.. image:: https://github.com/bensampson5/libsv/actions/workflows/ci.yml/badge.svg\n   :target: https://github.com/bensampson5/libsv/actions/workflows/ci.yml\n\n.. image:: https://readthedocs.org/projects/libsv/badge/?version=latest\n   :target: https://libsv.readthedocs.io/en/latest/?badge=latest\n   :alt: Documentation Status\n\nWelcome to LibSV! `Click here to go to LibSV’s\ndocumentation \u003chttps://libsv.readthedocs.io/en/latest/\u003e`_.\n\nLibSV is an open source, parameterized SystemVerilog digital hardware IP library.\nWhile similar libraries may already exist, LibSV is unique in that it takes advantage\nof open-source, state-of-the-art development best practices and tools from across the\nsoftware and digital design community, including:\n\n* Trivial installation. `LibSV is hosted on PyPI \u003chttps://pypi.org/project/libsv/\u003e`_ and can easily be installed using \n  `pip \u003chttps://pip.pypa.io/en/stable/\u003e`_ or whichever Python package manager of your choice.\n* Easy-to-use. Simply add ```include \"libsv/\u003cpath\u003e/\u003cto\u003e/\u003cmodule\u003e.sv\"`` to where you want to use a LibSV module and then add the\n  ``site-packages/`` folder, where LibSV was installed, to the include path when building your project.\n* Automated testbenches, written in Python, that use `pytest \u003chttps://github.com/pytest-dev/pytest\u003e`_ to run\n  `Cocotb \u003chttps://github.com/cocotb/cocotb\u003e`_ + `Verilator \u003chttps://github.com/verilator/verilator\u003e`_ under the hood for \n  simple and fast logic simulation\n* All testbenches output waveform files in FST format for viewing with `GTKWave \u003chttp://gtkwave.sourceforge.net/\u003e`_\n* `Extensive documention \u003chttps://libsv.readthedocs.io/en/latest/\u003e`_ using `Sphinx \u003chttps://www.sphinx-doc.org/en/master/\u003e`_\n* Automated formatting and lint checks using `Verible \u003chttps://github.com/google/verible\u003e`_\n* `Continuous integration (CI) workflows \u003chttps://github.com/bensampson5/libsv/actions\u003e`_ integrated with \n  `Docker \u003chttps://www.docker.com/\u003e`_\n* `LibSV Docker images \u003chttps://hub.docker.com/repository/docker/bensampson5/libsv\u003e`_ published to\n  `Docker Hub \u003chttps://hub.docker.com/\u003e`_\n\nGetting Started\n---------------\n\nLibSV is very easy to use. First, install the ``libsv`` package from PyPI:\n\n.. code-block:: bash\n\n  pip install libsv\n\nWe recommend using a Python virtual environment so that the installation is project-specific and\nisolated from the rest of your system.\n\nThen add the ``site-packages/`` folder, where LibSV was just installed, to your include path when building your\nproject so that your design tools can find LibSV.\n\nFinally, at the top of your design file where you want to use LibSV modules, for each module you want to use, add:\n\n.. code-block:: SystemVerilog\n\n  `include \"libsv/\u003cpath\u003e/\u003cto\u003e/\u003cmodule\u003e.sv\"\n\nRunning Testbenches\n-------------------\n\nRunning the LibSV testbenches require `Cocotb \u003chttps://github.com/cocotb/cocotb\u003e`_, \n`Verilator \u003chttps://github.com/verilator/verilator\u003e`_, and a number of other dependencies to be installed.\nInstead of trying to install everything manually on your machine, the easier and recommended way to run the\nLibSV testbenches is to use the pre-built \n`LibSV Docker images on Docker Hub \u003chttps://hub.docker.com/repository/docker/bensampson5/libsv\u003e`__ that have the\ncomplete set of LibSV developer tools already installed.\n\nTo use a LibSV Docker image, first you’ll need to install `Docker \u003chttps://www.docker.com/get-started\u003e`__, \nif you don’t already have it.\n\nNext, pull the latest LibSV Docker image:\n\n.. code-block:: bash\n\n  docker build --pull -f Dockerfile.dev \\\n    --build-arg UID=$(id -u) \\\n    --build-arg GID=$(id -g) \\\n    -t libsv .\n\nThen, start a new Docker container using the LibSV image and mount the project folder to the container:\n\n.. code-block:: bash\n\n  docker run --rm -it -v $(pwd):/code libsv\n\nFinally, within the Docker container, run ``pytest``:\n\n.. code-block:: bash\n\n  pytest\n\nThis will run all the LibSV testbenches for the entire library (*Warning: This may take a while!*).\n\nInstead, to list all the available LibSV testbenches, run:\n\n.. code-block:: bash\n\n  pytest --co\n\nThen, you can run an individual or subset of testbenches using the ``-k`` flag which will only run tests which\nmatch the given substring expression:\n\n.. code-block:: bash\n\n  pytest -k EXPRESSION\n\nEach testbench generates an associated ``.fst`` waveform file that is written to the ``build/`` directory and can be\nviewed using `GTKWave \u003chttp://gtkwave.sourceforge.net/\u003e`_.\n\nBugs/Feature Requests\n---------------------\n\nPlease use `LibSV's GitHub issue tracker \u003chttps://github.com/bensampson5/libsv/issues\u003e`_ to submit bugs or request features.\n\nContributing\n------------\n\nContributions are much welcomed and appreciated! Take a look at the \n`Contributing \u003chttps://libsv.readthedocs.io/en/latest/contributing.html\u003e`_ page to get started.\n\nLicense\n-------\n\nDistributed under the terms of the `MIT \u003chttps://github.com/bensampson5/libsv/blob/main/LICENSE\u003e`_ license, LibSV is free\nand open source software.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbensampson5%2Flibsv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbensampson5%2Flibsv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbensampson5%2Flibsv/lists"}