{"id":13537369,"url":"https://github.com/bespoke-silicon-group/basejump_stl","last_synced_at":"2025-04-02T04:30:40.769Z","repository":{"id":37431159,"uuid":"179529893","full_name":"bespoke-silicon-group/basejump_stl","owner":"bespoke-silicon-group","description":"BaseJump STL: A Standard Template Library for SystemVerilog","archived":false,"fork":false,"pushed_at":"2025-04-01T19:24:16.000Z","size":9301,"stargazers_count":563,"open_issues_count":167,"forks_count":105,"subscribers_count":29,"default_branch":"master","last_synced_at":"2025-04-01T20:27:22.499Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"http://bjump.org/","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/bespoke-silicon-group.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-04-04T15:52:33.000Z","updated_at":"2025-04-01T19:24:15.000Z","dependencies_parsed_at":"2023-10-17T03:03:41.007Z","dependency_job_id":"be0c8328-1b54-4d45-a3cb-49e6be97779b","html_url":"https://github.com/bespoke-silicon-group/basejump_stl","commit_stats":null,"previous_names":[],"tags_count":6,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbasejump_stl","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbasejump_stl/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbasejump_stl/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbasejump_stl/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/bespoke-silicon-group","download_url":"https://codeload.github.com/bespoke-silicon-group/basejump_stl/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246756851,"owners_count":20828778,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T09:00:58.216Z","updated_at":"2025-04-02T04:30:35.750Z","avatar_url":"https://github.com/bespoke-silicon-group.png","language":"SystemVerilog","funding_links":[],"categories":["Libraries","Verilog"],"sub_categories":[],"readme":"# BaseJump Standard Template Library (STL) Repository\n\nThis library is a comprehensive hardware library for SystemVerilog that seeks to\ncontain all of the commonly used HW primitives. \n\nSee this paper [docs/BaseJump_STL_DAC_2018_Camera_Ready.pdf](https://github.com/bespoke-silicon-group/basejump_stl/blob/master/docs/BaseJump_STL_DAC_2018_Camera_Ready.pdf)\nwhich describes the design and usage.\n\nPlease also see the [BSG SystemVerilog Style Guide](https://docs.google.com/document/d/1xA5XUzBtz_D6aSyIBQUwFk_kSUdckrfxa2uzGjMgmCU/edit#) which describes many of the conventions used in this library, including the variants of the valid/ready handshaking protocols.\n\nNote: bsg_misc/bsg_defines.sv contains many macros used by BaseJump STL. Make sure it is in your include path.\n\n## Contents\n\n* bsg_misc\n\n Lots of digital building blocks, like counters, reset timers, gray to binary coders, etc.\n \n* bsg_mem\n\nPortable SRAM and RF interfaces.\n\n* bsg_dataflow\n\nFor standalone modules involved in data plumbing. E.g. two-element fifos, fifo-to-fifo transfer engines,\nsbox units, compare_and_swap, and array pack/unpack.\n\n* bsg_async\n\nThis is for asynchronous building blocks, like the bsg_async_fifo, synchronizers, and credit counters.\n\nNote: for tapeouts, you will need to pay attention to the physical design and timing constraints for these components.\n\n* bsg_noc\n\nNetwork on chip implementations\n\n* bsg_cache\n\nReusable Cache implementation\n\n* bsg_link\n\nHigh speed off-chip communication link (over LVCMOS I/Os, can hit 1.2 Gbps per pin to FPGA).\n\nUnidirectional off-chip high-speed source synchronous communication interface. (also used as FPGA bridge).\n\n* bsg_clk_gen\n\nOpen source portable clock generator (all-standard cell)\n\n* bsg_tag\n\nHigh speed SPI-like interface for configuration state\n\n* bsg_dmc\n\nLPDDR1 Dram Controller and PHY.\nRequires advanced knowledge to tapeout.\n \n* bsg_test\n\nData, clock, and reset generator for test benches.\n\n* testing\n\n\nMirrors the other directories, with tests.\n\n* hard\n\nMirrors other directories, contains replacement files for specific process technologies.\n\n## Example Usage\n\nExample usage of these modules can be found in the [HammerBlade manycore repository](https://github.com/bespoke-silicon-group/bsg_manycore), the [BlackParrot Repository](https://github.com/black-parrot/black-parrot) and the [Basejump STL Testing](https://github.com/bespoke-silicon-group/basejump_stl/tree/master/testing) repository.\n\n## Contact\n\nEmail: taylor-bsg@googlegroups.com\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbespoke-silicon-group%2Fbasejump_stl","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbespoke-silicon-group%2Fbasejump_stl","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbespoke-silicon-group%2Fbasejump_stl/lists"}