{"id":13775591,"url":"https://github.com/bespoke-silicon-group/bsg_fakeram","last_synced_at":"2025-05-11T08:32:25.196Z","repository":{"id":45456758,"uuid":"208315118","full_name":"bespoke-silicon-group/bsg_fakeram","owner":"bespoke-silicon-group","description":"fakeram generator for use by researchers who do not have access to commercial ram generators","archived":false,"fork":false,"pushed_at":"2023-01-13T19:40:40.000Z","size":933,"stargazers_count":32,"open_issues_count":4,"forks_count":14,"subscribers_count":10,"default_branch":"master","last_synced_at":"2024-11-17T10:40:03.780Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/bespoke-silicon-group.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-09-13T17:38:12.000Z","updated_at":"2024-10-29T14:41:25.000Z","dependencies_parsed_at":"2023-02-09T16:46:14.066Z","dependency_job_id":null,"html_url":"https://github.com/bespoke-silicon-group/bsg_fakeram","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbsg_fakeram","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbsg_fakeram/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbsg_fakeram/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbsg_fakeram/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/bespoke-silicon-group","download_url":"https://codeload.github.com/bespoke-silicon-group/bsg_fakeram/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253539978,"owners_count":21924517,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-03T17:01:42.085Z","updated_at":"2025-05-11T08:32:24.871Z","avatar_url":"https://github.com/bespoke-silicon-group.png","language":"Python","funding_links":[],"categories":["Memory"],"sub_categories":[],"readme":"# BSG Black-box SRAM Generator\r\n\r\nThis project is desgined to generate black-boxed SRAMs for use in CAD flows\r\nwhere either an SRAM generator is not avaible or doesn't exist.\r\n\r\n## Setup\r\n\r\nThe black-box SRAM generator depends on lightly modified version of\r\n[Cacti](https://github.com/HewlettPackard/cacti) for area, power, and timing\r\nmodeling. To build this version of Cacti, simply run:\r\n\r\n```\r\n$ make tools\r\n```\r\n\r\n## Usage\r\n\r\n### Configuration File\r\n\r\nThe input to the BSG Black-box SRAM generator is a simple JSON file that\r\ncontains some information about the technology node you are targeting as well\r\nas the size and names of SRAMs you would like to generate. Below is an example\r\nJSON file that can be found in `./example_cfgs/freepdk45.cfg`:\r\n\r\n```\r\n{\r\n  \"tech_nm\": 45,\r\n  \"voltage\": 1.1,\r\n  \"metalPrefix\": \"metal\",\r\n  \"pinWidth_nm\": 70,\r\n  \"pinPitch_nm\": 140,\r\n  \"snapWidth_nm\": 190,\r\n  \"snapHeight_nm\": 1400,\r\n  \"flipPins\": True,\r\n  \"srams\": [\r\n    {\"name\": \"sram_32x32_1rw\", \"width\": 32, \"depth\":  32, \"banks\": 1},\r\n    {\"name\": \"sram_8x512_1rw\", \"width\":  8, \"depth\": 512, \"banks\": 1}\r\n  ]\r\n}\r\n```\r\n\r\n`tech_nm` - The name of the target technology node (in nm). Used in Cacti for\r\nmodeling PPA of the SRAM.\r\n\r\n`voltage` - Nominal operating voltage for the tech node.\r\n\r\n`metalPrefix` - The string that prefixes metal layers.\r\n\r\n`pinWidth_nm` - The width of the signal pins (in nm).\r\n\r\n`pinPitch_nm` - The minimum pin pitch for signal pins (in nm). All pins will\r\nhave a pitch that is a multuple of this pitch. The first pin will be a\r\nmultiple of this pitch from the bottom edge of the macro too.\r\n\r\n`snapWidth_nm` - (Optional : 1) Snap the width of the generated memory to a\r\nmultiple of the given value.\r\n\r\n`snapHeight_nm` - (Optional : 1) Snap the height of the generated memory to a\r\nmultiple of the given value.\r\n\r\n`flipPins` - (Optional : false) Flip the pins. If set to false then metal 1 is\r\nassumed to be vertical. This means that signal pins will be on metal 4 and the\r\nsupply straps (also on metal 4) will be horizontal. If set to true then metal 1\r\nis assumed to be horizontal. This means that signal pins will be on metal 3 and\r\nthe supply straps (on metal 4) will be vertical.\r\n\r\n`srams` - A list of SRAMs to generate. Each sram should have a `name`, `width`\r\n(or the number of bits per word), `depth` (or number of words), and `banks`.\r\n\r\n\r\n### Running the Generator\r\n\r\nNow that you have a configuration file, it is time to run the generator. The\r\nmain makefile target is:\r\n\r\n```\r\n$ make run CONFIG=\u003cpath to config file\u003e\r\n```\r\n\r\nIf you'd perfer, you can open up the Makefile and set `CONFIG` rather than\r\nsetting it on the command line.\r\n\r\nAll of the generated files can be found in the `./results` directory. Inside\r\nthis directory will be a directory for each SRAM which contains the .lef, .lib\r\nand v file (as well as some intermediate files used for Cacti).\r\n\r\n### Comparison with standard SRAMs generated with OpenRAM compiler\r\n\r\n#### Generated Fakerams (Eg:- fakeram130_1024x8)\r\n\r\n![](docs/images/fakeram.png)\r\n\r\n![](docs/images/fakeram_io.png)\r\n\r\n- The generated fakerams are 1rw RAMs \r\n- All pins are on the left side and they are all on Metal 3.\r\n- Pins:\r\n  - 1x chip enable \r\n  - 1x write enable\r\n  - 1x clock \r\n  - 1x address-in port\r\n  - 1x data-in-data-out port\r\n  - 1x write-mask-in port (bit masked).\r\n\r\n![](docs/images/fakeram_power.png)\r\n\r\n- Power rails are vertical (can be made horizontal in the config file) - Alternate VDD and GND rails.\r\n- Metal layers 1, 2, 3 and 4 are blocked, metal 5 is free for routing over.\r\n\r\n#### Standard SRAMs compiled with OpenRAM (Eg:- [sky130_sram_1kbyte_1rw1r_8x1024_8](https://github.com/efabless/sky130_sram_macros/tree/main/sky130_sram_1kbyte_1rw1r_8x1024_8))\r\n\r\n![](docs/images/openram.png)\r\n\r\n![](docs/images/openram_pins.png)\r\n\r\n- 1rw1r RAMs\r\n- Pins cover all 4 sides\r\n- I/O pins use Metal 3 (on left and right sides) \u0026 Metal 4 (on top and bottom sides)\r\n- Pins:\r\n  - 2x clock \r\n  - 2x chip select\r\n  - 1x write enable\r\n  - 2x address-in port\r\n  - 1x data-out port\r\n  - 1x data-in-data-out port\r\n  - 1x write-mask pin/port (byte masked)\r\n\r\n- Power pins are in a ring format along the macro edge utilizing Metal 3 (Horizontal) \u0026 Metal 4 (Vertical)\r\n- Metal layers 1, 2, 3 and 4 are blocked, metal 5 is free for routing over.\r\n\r\n\r\n\r\n## Feedback\r\n\r\nFeedback is always welcome! We ask that you submit a GitHub issue for any bugs,\r\nimprovements, or new features you would like to see. We are also receptive to\r\noutside contributions but please be mindful of sensitive information that is\r\ncommonly associated with licensed IP.\r\n\r\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbespoke-silicon-group%2Fbsg_fakeram","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbespoke-silicon-group%2Fbsg_fakeram","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbespoke-silicon-group%2Fbsg_fakeram/lists"}