{"id":13399054,"url":"https://github.com/bespoke-silicon-group/bsg_pipeclean_suite","last_synced_at":"2025-03-14T03:31:09.343Z","repository":{"id":97991177,"uuid":"167424617","full_name":"bespoke-silicon-group/bsg_pipeclean_suite","owner":"bespoke-silicon-group","description":null,"archived":false,"fork":false,"pushed_at":"2020-01-09T16:37:48.000Z","size":1324,"stargazers_count":11,"open_issues_count":0,"forks_count":2,"subscribers_count":5,"default_branch":"master","last_synced_at":"2024-07-31T19:17:56.616Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/bespoke-silicon-group.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2019-01-24T19:30:22.000Z","updated_at":"2024-07-22T19:42:06.000Z","dependencies_parsed_at":"2023-06-01T11:46:31.566Z","dependency_job_id":null,"html_url":"https://github.com/bespoke-silicon-group/bsg_pipeclean_suite","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbsg_pipeclean_suite","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbsg_pipeclean_suite/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbsg_pipeclean_suite/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bespoke-silicon-group%2Fbsg_pipeclean_suite/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/bespoke-silicon-group","download_url":"https://codeload.github.com/bespoke-silicon-group/bsg_pipeclean_suite/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":221432684,"owners_count":16820058,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-07-30T19:00:33.793Z","updated_at":"2024-10-25T14:32:24.786Z","avatar_url":"https://github.com/bespoke-silicon-group.png","language":"Verilog","funding_links":[],"categories":["Projects (sorted by year)","Benchmarks"],"sub_categories":["2019"],"readme":"# BSG Pipeclean Suite\n\nThis repository contains a collection of designs used to stress test new CAD\nflows. Each design is intended stress a different aspect of the CAD flow with\nincreasing complexity. The structure of each design is consistent to make it\neasy for CAD flows to find and link all required files for the design. For\nfurther details on how to get a design up and running, see the\n[Design Usage](#design-usage) section.\n\nThese designs make use of the [IDEA Dimensionless \n(IDF)](https://docs.google.com/document/d/1rIB81hEOSNs2F1pIF6WbIwSNe-8HbfEtZRlaMFKdhKk/edit?usp=sharing)\nspecification. Floorplan and timing constraint files are _dimensionless_\nmeaning that all units are expressed in terms of properties of the process\nrather than concrete units (such as microns or picoseconds). In-order to use\nthese designs, you will need access to basic PDK information such as the\nmetal layer stack properties and unit tile sizes as well as the [FO4 value](#fo4-calculation).\nFor easy integration of the floorplanning file into existing CAD flows, the IDF\nfloorplanning files can be converted to DEF files using the IDF-to-DEF converter\nprovided by the [BSG IDF Tools](https://github.com/bespoke-silicon-group/bsg_idf_tools). \n\n## Currently Available Designs\n\n| Design Name                     | Description                                                      | Number of Gates |\n|:-------------------------------:|:-----------------------------------------------------------------|:---------------:|\n| small_comb                      | small sized combinational only design                            | ~300            |\n| medium_comb                     | medium sized combinational only design                           | ~3K             |\n| large_comb                      | large sized combinational only design                            | ~30K            |\n| black_parrot_fe_only_2019_03_11 | Front-end of a 64-bit RISC-V Core with Cache Coherence Directory | ~20K            |\n| black_parrot_be_only_2019_03_11 | Back-end of a 64-bit RISC-V Core with Cache Coherence Directory  | ~35K            |\n| black_parrot_2019_03_11         | Full 64-bit RISC-V Core with Cache Coherence Directory           | ~125K           |\n| black_parrot_2019_03_28         | Full 64-bit RISC-V Core with Cache Coherence Directory           | ~65K            |\n\n## Design Structure\n\nDesigns are structured in a consistent manner to make it easy for CAD flows to find all required\nfiles. Each design should have the following file and directory structure:\n\n```\n\u003cdesign_name\u003e\n+-- Makefile\n+-- constraints.FO4.sdc\n+-- floorplan.idf.json\n+-- harden_me.v\n+-- macro_generate.py\n+-- pickled.v\n```\n\n| File                 | Description                                                                                                                                              |\n|:---------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------|\n| Makefile             | Makefile to facilitate in running _macro_generate.py_ and [IDF-to-DEF converter](https://github.com/bespoke-silicon-group/bsg_idf_tools) utility script. |\n| constraints.FO4.sdc  | SDC timing constraints which depends on the [FO4 value](#fo4-calculation) for the target process.                                                        |\n| floorplan.idf.json   | [IDF Floorplan](https://docs.google.com/document/d/1rIB81hEOSNs2F1pIF6WbIwSNe-8HbfEtZRlaMFKdhKk/edit?usp=sharing) constraints file.                      |\n| harden_me.v          | Additional design file that contains blocks that are intended to be hardened for correct quality-of-results (requires additional setup).                 |\n| macro_generate.py    | Used to call macro generators for the target process (requires additional setup).                                                                        |\n| pickled.v            | Main design RTL file that has been pickled into a single .v file.                                                                                        |\n\n## Design Usage\n\nThese designs are _dimensionless_ and process agnostic, therefore to properly integrate them into a CAD flow and get the expected\nquality-of-result (QoR) we need to re-dimensionalize the designs. For each design, you should do the following items and the\nexecute the Makefile in the design by simply running `$ make` while in the design directory.\n\n### Macro Generation (_macro_generate.py_)\n\nInside the IDF Floorplan file is a \"harden\" section which describes components in the design that are either macro blocks or\npre-synthesized gate netlists. For macro generation, there is a python script inside each design call _macro_generate.py_. The\nintention of this script is to read the IDF Floorplan file and use that info to call macro generators. However, macro generators\nare process specific therefore the user is required to setup the script to shell out the correct commands. A small amount of\nframework has been implemented in _macro_generate.py_ however it is up to the user to get the generators operational.\n\n### Harened Verilog Model (_harden_me.v_)\n\nIn-order to instantiate hardened blocks they must be instantiated properly in the RTL. This will be done inside\n`harden_me.v`. This file contains a collection of modules with synthesizable RTL models that are intended to\nbe replaced with the hardened instance (either a macro or pre-synthesized netlist). The user should use the RTL\nmodel to ensure that the semantics of the hardened block match what the design expects.\n\n### IDF to DEF Conversion\n\nThe easiest way to integrate the [IDF Floorplan](https://docs.google.com/document/d/1rIB81hEOSNs2F1pIF6WbIwSNe-8HbfEtZRlaMFKdhKk/edit?usp=sharing)\ninto a cad flow is to first convert it into a design exchange format (DEF) file. DEF files are standardized\nfloorplan files. By converting the IDF Floorplan to a DEF file, you will also be re-dimensionalizing the \nfloorplan. Therefore, you will need access to the PDK's technology file (.tf). In the Makefile for the design,\nset the `TECHNOLOGY_FILE` variable to the path of the PDK's technology file. When you run `$ make` one of the\nsteps is to run the IDF to DEF converter script. Alternatively, you can run `$ make TECHNOLOGY_FILE=\u003cpath\u003e` if\nyou do not want to modify the Makefile.\n\n## FO4 Calculation\n\nFor timing constraints, you will need to determine the fan-out-of-4 (FO4) value for your given process and\nset the environment variable `FO4` to the FO4 value for your PDK:\n\n```\n(bash)  export FO4=\u003cvalue\u003e\n(csh)   setenv FO4 \u003cvalue\u003e\n```\n\nTo calculate the FO4, it is highly recommended to use a SPICE simulation (we use Synopsys HSpice) with parasitic\nextracted standard cell models. The following circuit is what we use to calculate the FO4:\n\n![image](https://drive.google.com/uc?export=view\u0026id=1E3TDwMpNMGvCMUYx0UFR4Vp8miB60Wnl)\n\nThe actual FO4 value is the propagation delay for an inverter in the ring (averaged\nbetween the rising and falling propagation delay, triggered at (VDD-VSS)/2). It is \nimportant to use many stages to make sure that the signal propagating through the ring\noscillator is going from rail-to-rail. Anecdotal, 7-stages seems to be enough for most\ncases however it is always recommended to open up the waveform and verify that the\nsignal is reaching VDD and VSS.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbespoke-silicon-group%2Fbsg_pipeclean_suite","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbespoke-silicon-group%2Fbsg_pipeclean_suite","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbespoke-silicon-group%2Fbsg_pipeclean_suite/lists"}