{"id":13838331,"url":"https://github.com/bl0x/learn-fpga-amaranth","last_synced_at":"2025-07-10T21:32:26.595Z","repository":{"id":99837438,"uuid":"588375724","full_name":"bl0x/learn-fpga-amaranth","owner":"bl0x","description":"Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL","archived":false,"fork":false,"pushed_at":"2024-07-20T22:56:56.000Z","size":81,"stargazers_count":82,"open_issues_count":1,"forks_count":11,"subscribers_count":5,"default_branch":"main","last_synced_at":"2024-08-05T15:07:21.589Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/bl0x.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":".github/FUNDING.yml","license":"LICENSES/Apache-2.0","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null},"funding":{"ko_fi":"bl0x_"}},"created_at":"2023-01-13T00:52:03.000Z","updated_at":"2024-07-20T22:57:00.000Z","dependencies_parsed_at":"2024-01-15T18:47:05.283Z","dependency_job_id":null,"html_url":"https://github.com/bl0x/learn-fpga-amaranth","commit_stats":null,"previous_names":[],"tags_count":2,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bl0x%2Flearn-fpga-amaranth","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bl0x%2Flearn-fpga-amaranth/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bl0x%2Flearn-fpga-amaranth/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bl0x%2Flearn-fpga-amaranth/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/bl0x","download_url":"https://codeload.github.com/bl0x/learn-fpga-amaranth/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":225657376,"owners_count":17503548,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-04T15:01:51.274Z","updated_at":"2024-11-21T01:30:52.858Z","avatar_url":"https://github.com/bl0x.png","language":"Python","funding_links":["https://ko-fi.com/bl0x_"],"categories":["Python","Uncategorized"],"sub_categories":["Uncategorized"],"readme":"## learn-fpga (Amaranth HDL version)\n\nThis repository contains code to follow the excellent learn-fpga tutorial by Bruno Levy [from blinker to RISC-V](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md) using [Amaranth HDL](https://github.com/amaranth-lang/amaranth) instead of Verilog.\n\nThe tutorial starts from a very simple 'blink' example and will end with a fully functional RISC-V CPU core.\n\nThis code repository is only meant as a supplement to Bruno Levy's main repository. There are very few explanations in this repository that go beyond explaining certain aspects of Amaranth HDL. Please refer to the main tutorial for detailed information of every step of the implementation.\n\nUsing Amaranth HDL the code can certainly be simplified / restructured, but the aim of this project is to keep close to the original.\n\nNote: The repository is currently undergoing a transition to incorporate language changes from Amaranth HDL 0.5. If you want to use older Amaranth versions, check out the tag 'pre-amaranth-0.5'.\n\n### Board support\n\nSupport for the following boards is included:\n\n* Digilent Arty A7\n* Digilent CMOD A7\n* Digilent CMOD S7 (untested)\n* Sipeed tang nano 9k\n\nIf you don't have a board, you can still run the code in the Amaranth Python simulator.\n\n\n### Toolchain\n\nAmaranth HDL supports the following toolchains for the boards:\n\n* AMD/Xilinx Vivado, proprietary\n* F4PGA (former Symbiflow), using FLOSS tools (Yosys, Nextpnr)\n* Gowin, proprietary\n* Project Apicula (for Gowin FPGAs)\n\n\n### Running the simulation\n\nEach directory contains a `bench.py` file. This contains a test bench for the simulator. Run it like so:\n\n```\nsource env.sh        # Add directories to Python library path\ncd 01_blink\npython bench.py\n```\n\n\n### Building a firmware bitfile\n\nThe platform specific code is in the `boards` directory. To build e.g. step 5 for the Arty A7 board:\n\n```\nsource env.sh        # Add directories to Python library path\npython boards/digilent_arty_a7.py 5\n```\n\n\n### RISC-V assembler\n\nThis repository also contains a (minimal) RISC-V assembler written in Python in the `tools` directory.\n\n\n### UART connection\n\nDue to deviation of the internal oscillator frequency from the nominal value it is possible that the UART baudrate is not exactly the same as what is set in the code (by default 1 MBaud). In this case it helps to vary the receiver baudrate by +- 20% and check if reception works. If an oscilloscope is available, you can also measure the clock frequency by patching out the clock signal to one of the pins and measuring the signal period.\n\n#### Sipeed Tang Nano 9k\n\nThe built-in UART-USB converter does not work very well (at least not on Linux). For this reason, it is better to connect an external UART-USB converter to the Pins 53 (rx) and 54 (tx). When testing the receiver had to be tuned to between 900 kBaud and 960 kBaud.\n\n### Licensing\n\nThe files in this repository are licensed under the BSD-3-Clause license.\nExceptions are marked in the respective files.\nSee the files in the LICENSES directory for details.\n\n\n### Author\n\n* *Bastian Löher (bl0x)*\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbl0x%2Flearn-fpga-amaranth","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbl0x%2Flearn-fpga-amaranth","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbl0x%2Flearn-fpga-amaranth/lists"}