{"id":13773130,"url":"https://github.com/bogdanvuk/pygears","last_synced_at":"2026-04-05T18:37:27.828Z","repository":{"id":41571014,"uuid":"124890922","full_name":"bogdanvuk/pygears","owner":"bogdanvuk","description":"HW Design: A Functional Approach","archived":false,"fork":false,"pushed_at":"2023-06-26T09:11:47.000Z","size":17278,"stargazers_count":145,"open_issues_count":10,"forks_count":13,"subscribers_count":28,"default_branch":"master","last_synced_at":"2025-05-11T02:47:19.065Z","etag":null,"topics":["asic","design","fpga","functional","hardware","hdl","python","simulator"],"latest_commit_sha":null,"homepage":"https://www.pygears.org","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/bogdanvuk.png","metadata":{"files":{"readme":"README.rst","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":"docs/roadmap.org","authors":null}},"created_at":"2018-03-12T13:10:06.000Z","updated_at":"2025-03-05T01:34:52.000Z","dependencies_parsed_at":"2024-01-17T07:12:03.444Z","dependency_job_id":null,"html_url":"https://github.com/bogdanvuk/pygears","commit_stats":null,"previous_names":[],"tags_count":3,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bogdanvuk%2Fpygears","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bogdanvuk%2Fpygears/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bogdanvuk%2Fpygears/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/bogdanvuk%2Fpygears/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/bogdanvuk","download_url":"https://codeload.github.com/bogdanvuk/pygears/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253523690,"owners_count":21921815,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","design","fpga","functional","hardware","hdl","python","simulator"],"created_at":"2024-08-03T17:01:11.787Z","updated_at":"2026-04-05T18:37:27.790Z","avatar_url":"https://github.com/bogdanvuk.png","language":"Python","funding_links":[],"categories":["Circuit Compilers"],"sub_categories":[],"readme":"Welcome to PyGears \n==================\n\nHW Design: A Functional Approach\n--------------------------------\n\n**PyGears** is a free framework that lets you design hardware using high-level Python constructs and compile it to synthesizable SystemVerilog or Verilog code. There is a built-in simulator that lets you use arbitrary Python code with its vast set of libraries to verify your hardware modules. **PyGears** makes connecting modules easy, and has built-in synchronization mechanisms that help you build correct parallel systems.\n\n.. code-block:: python\n\n  @gear\n  def echo(samples: Fixp, *, feedback_gain, sample_rate, delay):\n\n      sample_dly_len = round(sample_rate * delay)\n      fifo_depth = ceil_pow2(sample_dly_len)\n      feedback_gain_fixp = samples.dtype(feedback_gain)\n\n      dout = Intf(samples.dtype)\n\n      feedback = decouple(dout, depth=fifo_depth) \\\n          | prefill(dtype=samples.dtype, num=sample_dly_len)\n\n      feedback_attenuated = (feedback * feedback_gain_fixp) \\\n          | samples.dtype\n\n      dout |= (samples + feedback_attenuated) | samples.dtype\n\n      return dout\n\nPython functions model hardware modules, where function arguments represent module inputs and parameters. Example ``echo`` module has a single input port called ``samples`` where data of arbitrary signed fixed-point type ``Fixp`` can be received. Other three parameters ``feedback_gain``, ``sample_rate`` and ``delay`` are compile time parameters.\n\n.. code-block:: python\n\n  @gear\n  def echo(samples: Fixp, *, feedback_gain, sample_rate, delay):\n      ...\n\nArbitrary Python code can be used in modules at compile time, for an example to transform input parameters:\n\n.. code-block:: python\n\n    sample_dly_len = round(sample_rate * delay)\n    fifo_depth = ceil_pow2(sample_dly_len)\n    feedback_gain_fixp = samples.dtype(feedback_gain)\n\nRest of the ``echo`` function code describes the hardware module for applying echo audio effect to the input stream. \n\n.. image:: images/echo.png\n    :align: center\n\nModules are instantiated using function calls: ``decouple(dout, depth=fifo_depth)``, which return module output interfaces that can in turn be passed as arguments to other module functions in order to make a connection between the modules. For conveniance the pipe ``\"|\"`` operator can be used to pass output of one function as argument to the next one. This was used to connect the output of ``decouple`` to ``prefill`` (``\"\\\"`` is used just to split the line visually):\n\n.. code-block:: python\n\n    feedback = decouple(dout, depth=fifo_depth) \\\n        | prefill(dtype=samples.dtype, num=sample_dly_len)\n\nAgain, the ``echo`` function returns its output interfaces which is then used to establish the connection with the next module that received the ``echo`` output stream:\n\n.. code-block:: python\n\n  @gear\n  def echo(...):\n      ...\n      return dout\n\nBuilt-in simulator makes it easy to test and verify the modules while drawing power from the Python vast ecosystem of libraries. For an example, use Python built-in `audioop \u003chttps://docs.python.org/3.7/library/audioop.html\u003e`_ library to read WAV files into an input samples stream for the ``echo`` module, and then visualise the input and output waveforms using `matplotlib \u003chttps://matplotlib.org/\u003e`_:\n\n.. image:: images/echo_plot.png\n\nSpeedup the simulation by configuring **PyGears** simulator to use open-source `Verilator \u003chttp://www.veripool.org/wiki/verilator\u003e`_ to simulate hardware modules, or some of the proprietary simulators like Questa, NCSim or Xsim. Implement any part of the system in a standard HDL and debug your design by inspecting the waveforms for an example in open-source wave viewer `GTKWave \u003chttp://gtkwave.sourceforge.net\u003e`_ \n\n.. image:: images/echo_vcd.png\n\nCheckout `Echo example description \u003chttps://www.pygears.org/echo.html#echo-examples\u003e`_ for more in depth information about the ``echo`` example.\n\nInstallation instructions\n~~~~~~~~~~~~~~~~~~~~~~~~~\n\nInstall **PyGears** package with the Python package manager. On Linux distributions, depending on how your Python was installed you might get an error and need to prefix the command with ``sudo``:\n\n.. code-block:: bash\n\n   pip3 install pygears\n\nFor more detailed installation instructions (including how to install additional software) checkout `Installation \u003chttps://www.pygears.org/install.html#install\u003e`_ page.\n\nRead the documentation\n~~~~~~~~~~~~~~~~~~~~~~\n\n`PyGears documentation \u003chttps://www.pygears.org/\u003e`_\n\nCheckout the examples\n~~~~~~~~~~~~~~~~~~~~~\n\n`Library of standard modules \u003chttps://www.pygears.org/gears/index.html\u003e`_\n\n`Echo \u003chttps://www.pygears.org/echo.html#echo-examples\u003e`_: Hardware module that applies echo audio effect to a continuous audio stream.\n\n`RISC-V processor \u003chttps://github.com/bogdanvuk/pygears_riscv\u003e`__: **PyGears** implementation. Checkout also the `RISC-V implementation blog series \u003chttps://www.pygears.org/blog/riscv/introduction.html\u003e`_.\n\n`Tests \u003chttps://github.com/bogdanvuk/pygears/tree/master/tests\u003e`_: Contain many examples on how individual **PyGears** components operate\n\nContributions\n-------------\n\nSpecial thanks to the people that helped develop this framework:\n\n- Andrea Erdeljan\n- Damjan Rakanović\n- Nemanja Kajtez\n- Risto Pejašinović\n- Stefan Tambur\n- Vladimir Nikić\n- Vladimir Vrbaški\n\nIn order to contribute, pull your copy from `github repository \u003chttps://github.com/bogdanvuk/pygears\u003e`_ and create a pull request.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbogdanvuk%2Fpygears","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbogdanvuk%2Fpygears","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbogdanvuk%2Fpygears/lists"}