{"id":17880363,"url":"https://github.com/brainstorm/rigolcsv2vcd","last_synced_at":"2025-04-03T01:17:11.322Z","repository":{"id":146072618,"uuid":"593591941","full_name":"brainstorm/rigolcsv2vcd","owner":"brainstorm","description":"Transforms Rigol's PLA2216 logic analyser probe CSV to VCD format","archived":false,"fork":false,"pushed_at":"2023-02-21T06:48:34.000Z","size":688,"stargazers_count":1,"open_issues_count":1,"forks_count":1,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-02-08T15:25:03.488Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Rust","has_issues":false,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/brainstorm.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-01-26T11:52:06.000Z","updated_at":"2023-01-29T21:50:14.000Z","dependencies_parsed_at":null,"dependency_job_id":"f24c107d-f2e9-4000-821c-65d9fdd203e7","html_url":"https://github.com/brainstorm/rigolcsv2vcd","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/brainstorm%2Frigolcsv2vcd","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/brainstorm%2Frigolcsv2vcd/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/brainstorm%2Frigolcsv2vcd/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/brainstorm%2Frigolcsv2vcd/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/brainstorm","download_url":"https://codeload.github.com/brainstorm/rigolcsv2vcd/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246916762,"owners_count":20854514,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-28T12:14:17.422Z","updated_at":"2025-04-03T01:17:11.294Z","avatar_url":"https://github.com/brainstorm.png","language":"Rust","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Rigol CSV to VCD converter\n\nThis (WIP) crate intends to transform the CSV output from a [Rigol PLA2216 logic analyser probe][PLA2216] to [VCD format][VCD].\n\n## Quickstart\n\n```shell\ncargo run --release \u003c data/test1.csv\n```\n\n## Data inputs/outputs\n\nFrom Rigol support:\n\n\u003e The instrument is combining LA channels D0-D7 together, so that channel 0 is bit 0 and channel 7 is bit 7, this would be the same for LA channels D8-D15.\n\nSo the goal is to convert this string data:\n\n```\nTime(s),D7-D0,D15-D8,t0 = -0.01s, tInc = 1e-09,\n-9.999999E-03,0.000000E+00,0.000000E+00,,\n-9.999998E-03,0.000000E+00,0.000000E+00,,\n(...)\n```\n\nTo vectors on the VCD output (not necessarily equivalent to the above CSV, just illustrative):\n\n```\n$timescale 1 ns $end\n$scope module top $end\n$var wire 16 # data $end\n$upscope $end\n$enddefinitions $end\n$dumpvars\nb0000000000000000 #\n$end\n#9999995\nb0000000000000001 #\n#9999996\nb0000000000000010 #\n#9999997\nb0000000000000011 #\n#9999998\nb0000000000000000 #\n#9999999\n```\n\n## Current status\nHow it started (Rigol oscilloscope screenshot):\n\n![Rigol oscilloscope 100Hz/200Hz baseline signal gen](./img/100_200Hz_signals_rigol.png)\n\nHot it's going (VCDs converted from CSV at different timescales):\n\n![Gtkwave reading VCD output 1](./img/gtkwave_baseline_2.png)\n![Gtkwave reading VCD output 2](./img/gtkwave_baseline_3.png)\n\nAs one can see, there's still some bugs to iron out (or report upstream).\n\n[PLA2216]: https://rigolshop.eu/accessories/probe/mso5000/pla2216.html\n[VCD]: https://en.wikipedia.org/wiki/Value_change_dump\n[python_1]: https://github.com/vidavidorra/rigol-csv-analyser\n[python_2]: https://github.com/carlos-jenkins/csv2vcd\n[1]: https://crates.io/crates/vcdump\n[2]: https://github.com/kevinmehall/rust-vcd\n[3]: https://crates.io/crates/vcd-ng\n[4]: https://crates.io/crates/vcd\n[5]: https://crates.io/crates/vcd_rust\n[vcd_rust_viz]: https://github.com/psurply/dwfv\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbrainstorm%2Frigolcsv2vcd","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbrainstorm%2Frigolcsv2vcd","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbrainstorm%2Frigolcsv2vcd/lists"}