{"id":49374419,"url":"https://github.com/brandonfromph/mirr-project","last_synced_at":"2026-04-28T01:34:17.382Z","repository":{"id":342783892,"uuid":"1175112550","full_name":"brandonfromph/mirr-project","owner":"brandonfromph","description":"MIRR is a hardware rule language for safety-critical systems. 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Places where a software bug or scheduling delay is not a crash report — it is a physical consequence.\n\n---\n\n## Example\n\nA neonatal respirator emergency clamp:\n\n```mirr\nmodule neonatal_respirator {\n    signal airway_pressure: in u16;\n    signal clamp_valve:     out bool;\n\n    guard sustained_pressure_drop {\n        when airway_pressure \u003c 50\n        for  1000 cycles;\n    }\n\n    reflex emergency_clamp {\n        on sustained_pressure_drop {\n            clamp_valve = true;\n        }\n    }\n}\n```\n\nIf `airway_pressure` stays below 50 for 1000 consecutive clock cycles, `clamp_valve` is set to `true`.\n\nThe compiler turns the `for 1000 cycles` rule into a shift register chain in hardware. There is no polling loop, no interrupt handler, no kernel — the hardware enforces the rule directly.\n\n---\n\n## Design philosophy\n\nMIRR occupies the space between C++ (no hardware timing primitives) and raw RTL (no safety abstractions). It enforces these guarantees at compile time:\n\n| Constraint | How it is enforced |\n|---|---|\n| Temporal correctness | Guards compile to shift registers, not software timers |\n| Bit-width safety | Width inference assigns minimum safe widths; unsafe truncation is a hard error |\n| No unsafe code | `#![forbid(unsafe_code)]` across all crates |\n| No unbounded loops | All passes are iterative with explicit bounds (NASA Power-of-10) |\n| Zero warnings | `#![deny(warnings)]` enforced in CI |\n\nThe language has exactly three constructs — **Signal**, **Guard**, **Reflex** — plus verification **Properties** and reusable **Patterns**. See the [Tutorial](docs/tutorial.md) for the full language guide.\n\n---\n\n## Living Research Artifact\n\nMIRR is published as a Living Research Artifact (LRA) — an interactive\npaper where the compiler runs live in the browser.\n\n**[Read the interactive paper](https://brandonfromph.github.io/mirr-project/paper/)**\n\nThe paper, the compiler, the Coq proofs, and the browser demos are one\nGPL-3.0 licensed artifact. The paper cannot be separated from the code\nand submitted to a journal under a Copyright Transfer Agreement without\nviolating the GPL already granted to the public.\n\nTo cite MIRR, use [`CITATION.cff`](CITATION.cff) or cite the commit\nhash of the version you used.\n\n**Want this format for your own paper?** Fork the\n[LRA Template](https://github.com/brandonfromph/lra-template) — a\nreusable, GPL-3.0 scaffold for interactive research papers.\nSee the [LRA-1.0 Specification](template/spec/LRA-1.0.md) for the\nformal standard.\n\nTo verify claims locally:\n\n```bash\n# Build and run the compiler\ncargo run --bin mirr-compile -- --emit verilog examples/tmr_sensor_fusion.mirr\n\n# Build the wasm demo\nrustup target add wasm32-unknown-unknown\ncargo install wasm-pack\nwasm-pack build crates/mirr-wasm --target web --out-dir ../../demos --release\n\n# Serve locally\ncd paper \u0026\u0026 python3 -m http.server 8080\n```\n\n### lra-cli\n\nThe `lra-cli` tool manages LRA projects from the command line. Install with\n`cargo install lra-cli`. Subcommands: `init`, `validate`, `serve`, `badge`,\n`build`.\n\n---\n\n## Getting started\n\n### Prerequisites\n\nYou need the Rust toolchain. Nothing else.\n\n```bash\ncurl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh\n```\n\n### Installation\n\n```bash\ngit clone https://github.com/brandonfromph/mirr-project.git\ncd mirr-project\ncargo build --release\ncargo test   # all tests should pass with zero warnings\n```\n\n---\n\n## Usage\n\n```bash\n# Compile to S-expression IR\ncargo run --bin mirr-compile -- examples/neonatal_respirator.mirr --emit sexpr\n\n# Full pipeline — emit SystemVerilog RTL\ncargo run --bin mirr-compile -- examples/neonatal_respirator.mirr --emit verilog\n\n# Other emit formats: json, dot, sva, firrtl, rspu\ncargo run --bin mirr-compile -- examples/neonatal_respirator.mirr --emit json\n```\n\n---\n\n## Documentation\n\n| Document | Description |\n|----------|-------------|\n| [Tutorial](docs/tutorial.md) | 10-lesson beginner guide — no hardware experience needed |\n| [Error Codes](docs/error_codes.md) | Complete catalogue of compiler diagnostics (E1xx–E8xx) |\n| [Type System](docs/type-system.md) | Signed/unsigned types, width inference, and error codes |\n| [R-SPU ISA Spec](docs/rspu_isa_spec.md) | R-SPU instruction set architecture and register file |\n| [Migration Guide](docs/migration-guide.md) | Upgrade notes for 0.1.0 to 0.3.0 |\n| [FPGA Targets Guide](docs/fpga-targets-guide.md) | Board support for iCE40, ECP5, Xilinx 7, Ultrascale, Gowin, Efinix |\n| [MAPE-K Guide](docs/mape-k-guide.md) | Autonomic Monitor–Analyze–Plan–Execute–Knowledge loop |\n| [S-Expression Guide](docs/sexpr-guide.md) | Homoiconic IR, reader macros, and bounded evaluation |\n| [Roadmap](docs/roadmap.md) | Phase 0–10 project roadmap |\n| [CHANGELOG](CHANGELOG.md) | Versioned change history |\n\n---\n\n## Roadmap\n\n- [x] Phase 0–6 — Foundation through integration pipeline\n- [x] Phase 7a — Safety properties and SVA assertion emission\n- [x] Phase 7b — Homoiconic pattern system (`def`/`reflect`)\n- [x] Phase 7 — Formal verification (Rocq proofs)\n- [x] Phase 8 — R-SPU instruction set architecture\n- [ ] Phase 9 — Multi-core fabric\n- [ ] Phase 10 — Production certification (DO-178C, IEC 62304, ISO 26262)\n\nSee [docs/roadmap.md](docs/roadmap.md) for the full technical specification of each phase.\n\n---\n\n## Contributing\n\nContributions are welcome — particularly from researchers in formal verification, hardware synthesis, and safety-critical systems. Read [docs/roadmap.md](docs/roadmap.md) to understand the architecture, then open an issue to discuss before writing code.\n\n1. Fork the project\n2. Create a feature branch (`git checkout -b feature/your-feature`)\n3. Commit your changes\n4. Open a Pull Request\n\nAll contributions must pass `cargo test`, `cargo clippy -- -D warnings`, and `cargo fmt --check`.\n\n---\n\n## License\n\nDistributed under the GPL-3.0 License. See [`LICENSE`](LICENSE) for the full terms.\n\n---\n\n## Contact \u0026 acknowledgments\n\nMIRR is a safety-critical HDL compiler targeting medical devices (FDA 21 CFR Part 11), aerospace (DO-178C), and automotive (ISO 26262) applications. It provides cryptographically signed build receipts for regulatory compliance and formal verification of temporal properties.\n\n**Built on the work of:**\n- Xiao et al. (2025) — [Cement2: Temporal Hardware Transactions](https://doi.org/10.48550/arXiv.2511.15073)\n- Li et al. (2025) — [SmaRTLy: RTL Optimization with Logic Inferencing](https://doi.org/10.48550/arXiv.2510.17251)\n- Wang et al. (2026) — [FIRWINE: Formally Verified Width Inference](https://doi.org/10.48550/arXiv.2601.12813)\n- Pnueli, A. (1977) — [The Temporal Logic of Programs](https://doi.org/10.1109/SFCS.1977.32)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbrandonfromph%2Fmirr-project","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbrandonfromph%2Fmirr-project","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbrandonfromph%2Fmirr-project/lists"}