{"id":20999883,"url":"https://github.com/brentseidel/sim-cpu","last_synced_at":"2025-05-14T23:31:21.639Z","repository":{"id":95368268,"uuid":"450574856","full_name":"BrentSeidel/Sim-CPU","owner":"BrentSeidel","description":"CPU Simulations written in Ada","archived":false,"fork":false,"pushed_at":"2025-04-13T19:23:10.000Z","size":2579,"stargazers_count":10,"open_issues_count":3,"forks_count":0,"subscribers_count":3,"default_branch":"main","last_synced_at":"2025-04-13T19:39:41.464Z","etag":null,"topics":["6502-emulation","68000","8080a","8085","ada","assembly-language","simulation","z80-emulator"],"latest_commit_sha":null,"homepage":"","language":"Ada","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/BrentSeidel.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2022-01-21T17:08:19.000Z","updated_at":"2025-04-13T19:23:13.000Z","dependencies_parsed_at":"2024-04-05T18:24:38.004Z","dependency_job_id":"a768239a-848c-4022-9206-5e1de927bbef","html_url":"https://github.com/BrentSeidel/Sim-CPU","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/BrentSeidel%2FSim-CPU","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/BrentSeidel%2FSim-CPU/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/BrentSeidel%2FSim-CPU/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/BrentSeidel%2FSim-CPU/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/BrentSeidel","download_url":"https://codeload.github.com/BrentSeidel/Sim-CPU/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254248189,"owners_count":22038981,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["6502-emulation","68000","8080a","8085","ada","assembly-language","simulation","z80-emulator"],"created_at":"2024-11-19T08:08:47.568Z","updated_at":"2025-05-14T23:31:16.562Z","avatar_url":"https://github.com/BrentSeidel.png","language":"Ada","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Sim-CPU\nCPU Simulations written in Ada\n\nThis is spun off of the Pi-Mainframe repository.  Moving simulation into\na separate repository will allow simulators to be developed more independently\nas well as used in other applications.\n\n[![Alire](https://img.shields.io/endpoint?url=https://alire.ada.dev/badges/bbs_simcpu.json)]\n(https://alire.ada.dev/crates/bbs_simcpu.html)\n\n\n[![Alire](https://img.shields.io/endpoint?url=https://alire.ada.dev/badges/simcpucli.json)]\n(https://alire.ada.dev/crates/simcpucli.html)\n\n\n[![Alire](https://img.shields.io/endpoint?url=https://alire.ada.dev/badges/loadcpm.json)]\n(https://alire.ada.dev/crates/loadcpm.html)\n\n\n## Implementation\nThe root of the simulators is the abstract object \"simulator\" defined in the\nBBS.Sim_CPU package.  It defined the external interface that all simulators\nmust implement.  It is expected to evolve as some actual CPU simulators get\nimplemented.\n\n## Simulators\nThe following simulators are implemented.\n\n### Simple Example\nThis is not really a CPU simulator.  Its main purpose is to blink the lights\nin the Pi-Mainframe in interesting patterns.\n\n### Intel 8080\n[More information](https://github.com/BrentSeidel/Sim-CPU/tree/main/src/i8080/README.md)\n\nAll 8080 and 8085 instructions have been implemented.  Z80 instructions are\nbeing implemented, but are not ready for use yet.\n\n### Motorola 68000\n[More information](https://github.com/BrentSeidel/Sim-CPU/tree/main/src/m68000/README.md)\n\nAll the 68000 CPU instructions have been implemented.\n\n## CLI\nA command line interface is provided for development of both the simulators\nand software that runs on the simulator.\n\nThe following commands are currently provided:\n-  BREAK \u003caddr\u003e\n    -    Set a breakpoint (currently only one can be active at a time)\n-  CONTINUE\n    -    Continue execution\n-  DEP \u003caddr\u003e \u003cvalue\u003e\n    -    Deposit value to a memory location\n-  DUMP \u003caddr\u003e\n    -    Display a region of memory\n-  EXIT or QUIT\n    -    EXIT the program\n-  GO \u003caddr\u003e\n    -    Start execution at a specified address\n-  LISP\n    -    Enter Lisp interpreter\n-  LOAD \u003cfilename\u003e\n    -    Load data from a file into memory\n-  REG\n    -    Display register values\n-  RUN\n    -    Execute instructions until halt or breakpoint\n-  STEP\n    -    Execute one instruction\n-  TRACE \u003clevel\u003e\n    -    Print information for each instruction executed\n-  UNBREAK \u003caddr\u003e\n    -    Remove a breakpoint\n\n### Lisp\nFor more information on the embedded [tiny-Lisp](https://github.com/BrentSeidel/Ada-Lisp)\ninterpreter.\n\nThe following additional Lisp words are implemented for controlling the\nsimulation.  With use, more words may be added.\n-  Execute one instruction\n    -  (sim-step)\n-  Get/set memory (byte/word/long)\n    -  (memb addr value)\n    -  (memb addr)\n    -  (memw addr value)\n    -  (memw addr)\n    -  (meml addr value)\n    -  (meml addr)\n-  Set execution address\n    -  (go address)\n-  Read register value (index is simulator dependent)\n    -  (reg-val index)\n-  Return number of registers\n    -  (num-reg)\n-  Return or set simulator halted state\n    -  (halted state)\n    -  (halted)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbrentseidel%2Fsim-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbrentseidel%2Fsim-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbrentseidel%2Fsim-cpu/lists"}