{"id":16795374,"url":"https://github.com/buaadreamer/buaa-co-2020","last_synced_at":"2025-04-11T00:06:12.182Z","repository":{"id":119819954,"uuid":"335828740","full_name":"BUAADreamer/BUAA-CO-2020","owner":"BUAADreamer","description":"2020年北航计组课设代码 This is the BUAA Computer Orgnization code project files.","archived":false,"fork":false,"pushed_at":"2022-01-27T03:19:04.000Z","size":42140,"stargazers_count":16,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-04-11T00:06:04.820Z","etag":null,"topics":["computer-organization","cpu","logisim","mars","mips","verilog"],"latest_commit_sha":null,"homepage":"","language":"Assembly","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/BUAADreamer.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-02-04T03:38:17.000Z","updated_at":"2025-02-23T15:39:45.000Z","dependencies_parsed_at":"2023-06-03T06:45:17.251Z","dependency_job_id":null,"html_url":"https://github.com/BUAADreamer/BUAA-CO-2020","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/BUAADreamer%2FBUAA-CO-2020","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/BUAADreamer%2FBUAA-CO-2020/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/BUAADreamer%2FBUAA-CO-2020/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/BUAADreamer%2FBUAA-CO-2020/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/BUAADreamer","download_url":"https://codeload.github.com/BUAADreamer/BUAA-CO-2020/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248317707,"owners_count":21083528,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["computer-organization","cpu","logisim","mars","mips","verilog"],"created_at":"2024-10-13T09:16:09.907Z","updated_at":"2025-04-11T00:06:12.153Z","avatar_url":"https://github.com/BUAADreamer.png","language":"Assembly","funding_links":[],"categories":[],"sub_categories":[],"readme":"# BUAA-CO-2020\n2020年秋季北航计组代码。This is My BUAA Computer Orgnization code project files.\n\n## introduction\n由于2020年秋季的北航计组实验由于时间冲突的原因只开课开到P7，P8没有开放，笔者很幸运地通关了，在这里还是放一下本菜鸡的代码，纪念一下那些熬夜奋战的时光\n\n北航的计组课程目标是开发支持`MIPS`指令集的CPU，在这个过程中学习数字电路，汇编语言，计算机软硬件组成等基础知识。\n\n## about Code\n### Pre 基础知识学习\n主要是`logisim`，`verilog`，`MIPS`以及相关工具（`ISE，Mars`等）的基本使用，为之后的各个Project打基础\n\n### P0 logisim搭建基本电路\n利用logisim搭建一些小的元件和状态机，难点主要在状态机搭建，要区分好`Moore`和`Mealy`\n\n### P1 verilog搭建基本电路\nP1和P0内容差不多，只是工具变了，主要就是用verilog搭建小元件和状态机\n\nP1课上**初始化**一定要注意！！！笔者就是在课上因为没有对一些变量初始化挂了一次。\n\n### P2 MIPS汇编语言\n基本就是用MIPS写一些基本的简单算法题，如果有类似快排，二分查找这样的复杂一些的算法题会给参考的C源代码\n\n课上难一些的也就是考**递归**算法翻译题,其他题基本都比较简单\n\n### P3 logisim单周期CPU开发(8条指令)\n课下:利用logisim搭建一个支持`{addu, subu, ori, lw, sw, beq, lui, nop}`指令集的单周期CPU\n\n课上:扩展给定的指令\n\n### P4 Verilog单周期CPU开发(10条指令)\n课下:利用Verilog搭建一个支持`{addu, subu, ori, lw, sw, beq, lui, jr,nop,jal}`指令集的单周期CPU\n\n课上:扩展给定的指令\n\n### P5 Verilog简单流水线CPU开发(11条指令)\n课下:利用Verilog搭建一个支持`{ addu, subu, ori, lw, sw, beq, lui, j, jal, jr, nop }`指令集的流水线CPU\n\n课上:扩展给定的指令\n\n### P6 Verilog复杂流水线CPU开发(51条指令)\n课下:利用Verilog搭建一个支持`{LB、LBU、LH、LHU、LW、SB、SH、SW、ADD、ADDU、SUB、 SUBU、 MULT、 MULTU、 DIV、 DIVU、 SLL、 SRL、 SRA、SLLV、SRLV、SRAV、AND、OR、XOR、NOR、ADDI、ADDIU、ANDI、ORI、XORI、LUI、SLT、SLTI、SLTIU、SLTU、BEQ、BNE、BLEZ、BGTZ、BLTZ、BGEZ、J、JAL、JALR、JR、MFHI、MFLO、MTHI、MTLO}`指令集的流水线CPU\n\n课上:扩展给定的指令\n\n### P7 Verilog处理器系统设计_支持中断异常(54条指令)\n课下:在P6的基础上新增`{eret,mfc0,mtc0}`三条中断/异常相关指令，新增异常处理模块，系统桥模块和定时器模块，和原本的CPU组成一个系统。\n\n课上:强测+扩展一条简单的异常中断指令(后者不一定会出现)\n\n### TestData\n自己构造，或者从github收集，或者同学提供的测试数据，以及部分测试脚本\n注：数据仅供参考，每年题目都可能会变化\n\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbuaadreamer%2Fbuaa-co-2020","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbuaadreamer%2Fbuaa-co-2020","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbuaadreamer%2Fbuaa-co-2020/lists"}