{"id":17464364,"url":"https://github.com/buhe/study_fpga","last_synced_at":"2025-10-17T21:06:38.991Z","repository":{"id":76742991,"uuid":"450724026","full_name":"buhe/study_fpga","owner":"buhe","description":"💾 fpga study with open source tools (on macos)","archived":false,"fork":false,"pushed_at":"2022-06-05T04:31:52.000Z","size":3471,"stargazers_count":3,"open_issues_count":1,"forks_count":0,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-02-02T08:17:19.044Z","etag":null,"topics":["chisel","chisel3","fpga","hardware","tang-nano","verilog"],"latest_commit_sha":null,"homepage":"","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/buhe.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-01-22T05:16:02.000Z","updated_at":"2024-10-17T09:44:16.000Z","dependencies_parsed_at":null,"dependency_job_id":"b4276009-1a81-478c-9132-91d3a8f6f5fe","html_url":"https://github.com/buhe/study_fpga","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/buhe%2Fstudy_fpga","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/buhe%2Fstudy_fpga/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/buhe%2Fstudy_fpga/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/buhe%2Fstudy_fpga/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/buhe","download_url":"https://codeload.github.com/buhe/study_fpga/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":245985789,"owners_count":20705069,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel","chisel3","fpga","hardware","tang-nano","verilog"],"created_at":"2024-10-18T10:45:34.107Z","updated_at":"2025-10-17T21:06:33.956Z","avatar_url":"https://github.com/buhe.png","language":"Scala","funding_links":[],"categories":[],"sub_categories":[],"readme":"## Fpga study with open source software (on macos)\n\n### Target\n\n- [x] yosys: flash to hardware\n- [ ] add logic\n- [ ] blink: chisel to verilog\n- [x] blink: use yosys flah to hardware\n- [ ] a clock: i2c\n- [ ] riscv64 cpu\n\n### Hardware\n\n- tang nano 4k\n- tang nano 9k\n\n### Resources\n\n- [数电 simplified chinese ](https://www.bilibili.com/video/BV1aJ411R7Hd)\n- [verilog simplified chinese ](https://www.bilibili.com/video/BV12y4y1v7V3)\n- https://www.xuetangx.com/course/THU08081000386/10322165?channel=i.area.learn_title\n- https://github.com/buhe/fpga_study/blob/main/docs/chisel-book-chinese.pdf\n- https://open.163.com/newview/movie/free?pid=M7A8MMH3M\u0026mid=M7A8O2HFQ\n- https://saiankit30.medium.com/how-to-simulate-verilog-models-on-macos-5a6f821b2c4f\n\n```bash\npip install -U apio\n```\n\n### Simulate\n#### Tools\n```bash\nbrew install icarus-verilog\nbrew install --cask gtkwave\n```\n#### Execute\n```bash\niverilog -o sample_tb.vvp sample_tb.v\nvvp sample_tb.vvp\n\nopen -a gtkwave\n```\n\n### ✅ Flash to fpga\n\n```bash\nbrew install yosys\npip install apycula\nbrew install openfpgaloader --HEAD\n\n# install nextpnr\nbrew install eigen\n# https://github.com/YosysHQ/nextpnr#nextpnr-gowin\ncmake . -DARCH=gowin\nmake -j$(nproc)\nsudo make install\n```\n\n### ✅ Verilog\n```bash\nyosys -D LEDS_NR=8 -p \"read_verilog blinky.v; synth_gowin -json blinky.json\"\nnextpnr-gowin --json blinky.json --write pnrblinky.json --device GW1NSR-LV4CQN48PC6/I5 --cst tangnano4k.cst\ngowin_pack -d GW1NSR-LV4CQN48PC6/I5 -o pack.fs pnrblinky.json\nopenFPGALoader -b tangnano4k pack.fs\n```\n[video](https://youtube.com/shorts/uIiRk0R6xPE)\n\n### Chisel\n```bash\nmake led_v\nyosys -p \"synth_gowin -top Led -json blinky.json\" output/Led.v\n\nnextpnr-gowin --json blinky.json --write pnrblinky.json --device GW1NSR-LV4CQN48PC7/I6 --cst examples/tangnano4k.cst\n\ngowin_pack -d GW1NSR-LV4CQN48PC7/I6 -o pack.fs pnrblinky.json\n\n```\n\n just need to specify how many LEDs your board has. For example for my TangNano with three LEDs:\n\n```bash\nyosys -D LEDS_NR=3 -p \"synth_gowin -json blinky.json\" blinky.v\n```\n\nso,9k is LEDS_NR=6,look up 9k.cst\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbuhe%2Fstudy_fpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fbuhe%2Fstudy_fpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fbuhe%2Fstudy_fpga/lists"}