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returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["16-bit","cmod-s7","cpu","fpga","iverilog","verilog","vintage","vivado"],"created_at":"2024-11-11T18:27:01.715Z","updated_at":"2026-02-19T14:01:56.230Z","avatar_url":"https://github.com/calint.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# zen-one\n\n\u003e :bell: experiments continued in project [riscv](https://github.com/calint/riscv)\n\nexperimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent\n\nthird try at fpga with verilog and vivado\n\nsame toy 16 bit retro cpu as [zen-x](https://github.com/calint/zen-x) but re-written\n* ad-hoc pipeline where the next instruction is fetched while current is executed\n* ad-hoc pipeline resolution for register being loaded from RAM and used by current instruction\n* dual-port RAM instead of ROM and RAM\n* one cycle per instruction for ALU, load and store\n* two cycles for load immediate\n* two cycles for call and jump if branch taken\n* two cycles for instructions that also return from current call\n* all core components run on positive edge of the clock\n\n```\n                          \n                          \n                       z   n - r   c      vintage 16 bit cpu\n                       e   e   e   a \n                       r   g   t   l      64K 16 bit ram\n                       o   a   u   l      16  16 bit registers\n                           t   r          64  calls stack\n                           i   n          66  MHz\n                           v              \n                           e\n\n                     | 0 | 1 | 2 | 3 |   4 - 7   | 8-11 | 12-15|        \n                     |---|---|---|---|-----------|------|------|        \n                     | z | n | r | c |   op      | rega | regb |        \n                     |---|---|---|---|---|-------|------|------|--------\n                     / . / . / . / 0 / 0 / 0 0 0 / .... / .... /  add  /\n                    / . / . / . / 0 / 0 / 1 0 0 / .... / .... /  sub  / \n                   / . / . / . / 0 / 0 / 0 1 0 / .... / .... /  or   / \n                  / . / . / . / 0 / 0 / 1 1 0 / .... / .... /  xor  / \n                 / . / . / . / 0 / 0 / 0 0 1 / .... / .... /  and  / \n                / . / . / . / 0 / 0 / 1 0 1 / ...  / .... /  not  / \n               / . / . / . / 0 / 0 / 0 1 1 / .... / .... /  cp   / \n              / . / . / . / 0 / 0 / 1 1 1 / imm4 / .... /  shf  / \n             /---/---/---/---/---/-------/------/------/-------/ \n            / . / . / . / 0 / 1 / 0 0 0 / imm4 / .... /  addi / \n           / . / . / . / 0 / 1 / 1 0 0 / 0000 / .... /  ldi  / \n          / . / . / . / 0 / 1 / 0 1 0 / src  / dst  /  ld   / \n         / . / . / . / 0 / 1 / 1 1 0 / dst  / src  /  st   / \n        / . / . / . / 0 / 1 / 0 0 1 / .... / .... /       / \n       / . / . / . / 0 / 1 / 1 0 1 / .... / .... /       / \n      / . / . / . / 0 / 1 / 0 1 1 / .... / .... /       / \n     / . / . / . / 0 / 1 / 1 1 1 / .... / .... /       / \n    /---/---/---/---/---/-------/------/------/-------/ \n   / . / . / 0 / 1 /    immediate 12 \u003c\u003c 4    /  call / \n  / . / . / 1 / 1 /   signed immediate 12   /  jmp  / \n /---/---/---/---/---/-------/------/------/-------/ \n \\ . \\ . \\ . \\ 0 \\ 1 \\ 1 0 0 \\ 0100 \\ .... \\  wl   \\\n  \\ . \\ . \\ . \\ 0 \\ 1 \\ 1 0 0 \\ 0101 \\ .... \\  wh   \\\n   \\ . \\ . \\ . \\ 0 \\ 1 \\ 1 0 0 \\ 0110 \\ .... \\  rl   \\\n    \\ . \\ . \\ . \\ 0 \\ 1 \\ 1 0 0 \\ 0111 \\ .... \\  rh   \\\n     \\ . \\ . \\ . \\ 0 \\ 1 \\ 1 0 0 \\ 1100 \\ .... \\       \\\n      \\ . \\ . \\ . \\ 0 \\ 1 \\ 1 0 0 \\ 1101 \\ .... \\       \\\n       \\ . \\ . \\ . \\ 0 \\ 1 \\ 1 0 0 \\ 1110 \\ .... \\ led   \\\n        \\ . \\ . \\ . \\ 0 \\ 1 \\ 1 0 0 \\ 1111 \\ imm4 \\ ledi  \\\n \n\n  op  :       : cyc |\n -----:-------:-----:--------------------------------------\n 0000 : add   :  1  : reg[b] += reg[a]\n 0010 : sub   :  1  : reg[b] -= reg[a] \n 0100 : or    :  1  : reg[b] |= reg[a] \n 0110 : xor   :  1  : reg[b] ^= reg[a] \n 1000 : and   :  1  : reg[b] \u0026= reg[a] \n 1010 : not   :  1  : reg[b] = ~reg[a] \n 1100 : cp    :  1  : reg[b] = reg[a]\n 1110 : shf   :  1  : reg[b] \u003e\u003e= (imm4\u003e=0?++imm4:-imm4)\n -----:-------:-----:--------------------------------------\n 0001 : addi  :  1  : reg[b] += (imm4\u003e=0?++imm4:-imm4)\n 0011 : ldi   :  2  : reg[b] = { next instruction }\n 0101 : ld    :  1  : reg[b] = ram[a]\n 0111 : st    :  1  : ram[a] = reg[b]\n 1001 :       :     : \n 1011 :       :     :\n 1101 :       :     :\n 1111 :       :     : \n -----:-------:-----:--------------------------------------\n\n  rc  :       : cyc :\n -----+-------+-----+--------------------------------------\n  01  : call  : 1-2  : pc = imm12 \u003c\u003c 4\n  11  : jmp   : 1-2  : pc += signed imm12\n -----+-------+-----+--------------------------------------\n\ni/o\n |z|n|r|c| op |rega|regb| mnemo | description\n |-+-+-+-+----+----+----+-------+--------------------------------------\n |.|.|.|0|1100|0100|....|  wl   | uart blocking write lower regs[b]\n |.|.|.|0|1100|0101|....|  wh   | uart blocking write higher regs[b]\n |.|.|.|0|1100|0110|....|  rl   | uart blocking read lower regs[b]\n |.|.|.|0|1100|0111|....|  rh   | uart blocking read higher regs[b]\n |.|.|.|0|1100|1100|....|       | \n |.|.|.|0|1100|1101|....|       | \n |.|.|.|0|1100|1110|....|  led  | sets leds to lower 4 bits of regs[b]\n |.|.|.|0|1100|1111|imm4|  ledi | sets leds to imm4\n\nzn flags in instructions are compared with current flags\ninstruction executes according to:\n * zn=11 : always\n * zn=00 : positive number\n * zn=10 : zero\n * zn=01 : negative number\n\ninstructions with rc=10 return from call\n\nhow-to with Vivado v2023.1:\n * to program device edit path to RAM file in \"zen-one.srcs/sources_1/new/SoC.v\"\n * connect fpga board Cmod S7 from digilent.com\n * run synthesis, run implementation, program device\n * find out which tty is on the usb connected to the card (e.g. /dev/ttyUSB1)\n * connect with terminal at 9600 baud, 8 bits, 1 stop bit, no parity \n * button 0 is reset, click it to restart and display the prompt\n * \"HELLO\" is the prompt\n * after the prompt the program enters a read / write loop (echo)\n \nprogramming zen-x\n * use 'zasm' to compile assembler code\n * see 'zen-one.srcs/sources_1/new/init.zasm' for examples\n\n```","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcalint%2Fzen-one","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcalint%2Fzen-one","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcalint%2Fzen-one/lists"}