{"id":50538066,"url":"https://github.com/carledwards/go6sim","last_synced_at":"2026-06-03T18:00:37.116Z","repository":{"id":355312009,"uuid":"1222118102","full_name":"carledwards/go6sim","owner":"carledwards","description":"6502 Simulator","archived":false,"fork":false,"pushed_at":"2026-05-25T23:16:21.000Z","size":42599,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-05-26T01:18:27.882Z","etag":null,"topics":["6502","6502-tools","foxpro"],"latest_commit_sha":null,"homepage":"https://carledwards.github.io/go6sim/","language":"Go","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/carledwards.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":"docs/roadmap.md","authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2026-04-27T04:03:01.000Z","updated_at":"2026-05-25T23:16:25.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/carledwards/go6sim","commit_stats":null,"previous_names":["carledwards/6502-sim-tui","carledwards/go6sim"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/carledwards/go6sim","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carledwards%2Fgo6sim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carledwards%2Fgo6sim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carledwards%2Fgo6sim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carledwards%2Fgo6sim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/carledwards","download_url":"https://codeload.github.com/carledwards/go6sim/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carledwards%2Fgo6sim/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":33876328,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-26T15:22:16.424Z","status":"online","status_checked_at":"2026-06-03T02:00:06.370Z","response_time":59,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["6502","6502-tools","foxpro"],"created_at":"2026-06-03T18:00:35.791Z","updated_at":"2026-06-03T18:00:37.109Z","avatar_url":"https://github.com/carledwards.png","language":"Go","funding_links":[],"categories":[],"sub_categories":[],"readme":"# go6sim\n\nA floating-window 6502 microcomputer simulator with two interchangeable\nCPU cores, a memory-mapped VIC video chip, a real **6522 VIA** peripheral\nticking on its own crystal, and a small library of demo programs. Built\non top of [`foxpro-go`](https://github.com/carledwards/foxpro-go)\n(FoxPro-for-DOS-style TUI framework) and\n[`6502-netsim-go`](https://github.com/carledwards/6502-netsim-go)\n(transistor-level [Visual6502](https://github.com/trebonian/visual6502) port). Each component plugs into a shared\nbus at hardware-realistic chip-select boundaries; each gets its own\ndraggable window.\n\nThe point is to make a 6502 system you can *see*: every memory access,\nevery register, every framebuffer cell, every timer underflow, in real\ntime. Long-term goal: a teaching tool where demos written here transfer\nto real silicon unmodified.\n\n## Screenshots\n\n**TUI Logic Analyzer** — bus + control-line trace in a real terminal,\ncaptured at 20 Hz with single-step granularity.\n\n![TUI Logic Analyzer](docs/images/tui_logic_analyzer.gif)\n\n**Wasm Logic Analyzer** — same widget rendered to a browser canvas\nvia the pixel-overlay path; ~8× the sample density per cell.\n\n![Wasm Logic Analyzer](docs/images/wasm_logic_analyzer.gif)\n\n**Wasm Emulation** — the full simulator running in a browser tab:\nCPU window, memory viewer, Monitor REPL, and the VIC graphics demo\nall driven by the same backend that runs in the terminal.\n\n![Wasm Emulation](docs/images/wasm_emu.gif)\n\n**Remote CPU, in the terminal** — the TUI started with\n`-cpu=remote`. RAM, ROM, VIA, and the framebuffer live here; the\nCPU itself is the Visual 6502 transistor sim running in a browser\ntab, talking back over a WebSocket. The CPU window flips from\n\"waiting\" to live the instant the browser page connects.\n\n![Remote CPU in the TUI](docs/images/tui_remote_cpu.gif)\n\n**Visual 6502 view** — the browser build (the same `wasm_emu.gif`\nmachine above) with the Visual 6502 window open. It's a live,\ntransistor-level rendering of the actual 6502 die — every one of\nthe chip's ~3,500 transistors, drawn from the original\n[Visual6502](https://github.com/trebonian/visual6502) project's\npolygon data — lit up node-by-node as your code executes. Click\nthe chip to flip on labelled annotations for the pin pads and\ninternal register blocks.\n\n![Visual 6502 in the browser](docs/images/wasm_visual6502.gif)\n\n## Quickstart\n\n```bash\nmake tidy\nmake run\n```\n\n`go.mod` pins\n[`foxpro-go`](https://github.com/carledwards/foxpro-go) (TUI framework)\nand [`6502-netsim-go`](https://github.com/carledwards/6502-netsim-go)\n(transistor-level CPU) to tagged versions, so a clean clone fetches\neverything from the module proxy with no sibling-checkout setup.\n\nIf you want to iterate on either dependency locally, add a temporary\n`replace` directive in `go.mod` pointing at your sibling checkout —\nremove it before pushing.\n\nDefaults are tuned for \"open it, see something happening\": the TUI\nboots on the interpretive CPU at Max speed with batch auto-tuned to\nfit the per-tick budget, the marquee demo is loaded, and the clock\nis running. Esc or Ctrl+Q to quit.\n\n## Browser build\n\nSame code, same demos, same dual-CPU backend, same VIA — running in\nthe browser via WebAssembly through\n[`foxpro-go/wasm`](https://github.com/carledwards/foxpro-go). The\nsimulator's `tcell.Screen` is swapped for a `tcell.SimulationScreen`\n(pure-Go cell buffer) and the JS side renders cells to a canvas.\nGraphics-mode pixels are layered onto the cell grid via a sentinel-\nrune trick — windows, drop shadows, and z-order all work over the\nbitmap.\n\n```bash\nmake wasm           # build web/sim.wasm + copy wasm_exec.js\nmake wasm-serve     # python3 -m http.server on port 8765 (override with PORT=)\n```\n\nThen open `http://localhost:8765/`.\n\nThe wasm build defaults to:\n\n- **interp** CPU (netsim is slow under wasm; swap via the CPU menu if\n  you want to watch transistors crawl)\n- auto-start running so visitors see motion immediately\n- BouncingBalls graphics demo as the boot program\n- Esc / Ctrl+Q disabled (would terminate the wasm runtime and brick\n  the page); close the tab instead\n\nBundle size: ~5.3 MB raw, ~1.4 MB gzipped. Standard static-host MIME\nconfig (`application/wasm`) is enough — no cross-origin headers\nrequired.\n\n## Bridge protocol + Monitor REPL\n\nBeyond the on-screen widgets, the simulator exposes a debugger\nprotocol — JSON-RPC 2.0 over NDJSON/TCP for remote drivers, or as\ndirect Go calls in-process. Both share one Go interface\n(`bridge.Target`), so the same Monitor REPL drives every edge:\n\n| Edge | Command | How it talks to the sim |\n|---|---|---|\n| Built-in Monitor (terminal) | `cmd/6502-sim` (Window → Toggle Monitor) | in-process via `bridge.HubDirect` |\n| Built-in Monitor (browser) | `cmd/6502-wasm` (Monitor visible by default) | in-process via `bridge.HubDirect` |\n| Headless bridge server | `cmd/6502-sim-serve` | listens on `:6502`, NDJSON/TCP |\n| Shared-bridge TUI | `cmd/6502-sim --serve` | TUI runs locally + accepts remote bridge clients |\n| Remote controller TUI | `cmd/6502-control` | dials a bridge server, healing reconnect |\n| **Future** | MCP server, VS Code extension, etc. | implement `bridge.Target` |\n\nThe Monitor itself lives in `internal/monitor`. Its command set:\n\n| Group | Verbs |\n|---|---|\n| CPU \u0026 run | `r` regs · `g [addr]` run · `s [n]` step · `.` stop · `reset` · `stack [r]` |\n| Memory | `m [addr] [n]` hex · `d [addr] [n]` disasm · `: \u003caddr\u003e \u003cb\u003e…` poke · `f \u003cs\u003e \u003ce\u003e \u003cb\u003e` fill · `t \u003cs\u003e \u003cd\u003e \u003cn\u003e` transfer · `h \u003cs\u003e \u003ce\u003e \u003cb\u003e…` hunt |\n| Breakpoints | `bp \u003caddr\u003e` · `bc [id\\|all]` · `bl` |\n| Interrupts | `irq` · `nmi` |\n| Hardware | `hw` / `info` · `via \u003csub\u003e` (list/dump/set) |\n| Monitor | `cls` · `help [cmd]` · `help window` · `reconnect` · `q` |\n\nAddresses are hex (`$E000` / `0xE000` / `E000`) or **symbolic**:\n`pc`, `sp`, `reset`, `irq`, `nmi`. The symbolic forms read live —\n`d pc` disassembles wherever you currently are; `m irq` dumps the\nIRQ handler the CPU would jump to right now.\n\nThe remote controller auto-reconnects with backoff if the sim\nrestarts. CPU state preservation across reconnect depends on which\nloader: `cmd/6502-sim --serve` keeps the live Hub across reconnects;\n`cmd/6502-sim-serve`'s per-session Hub is fresh on each reconnect.\n\nThe protocol contract lives in [`docs/bridge-v2.md`](docs/bridge-v2.md).\n\n### CLI flags (terminal build only)\n\n| Flag           | Default   | Notes                                                 |\n|----------------|-----------|-------------------------------------------------------|\n| `-cpu`         | `interp`  | CPU backend: `interp` or `netsim` (transistor)        |\n| `-run`         | `true`    | Start the clock running immediately                   |\n| `-speed`       | `max`     | Initial clock target: `1`, `10`, `20`, `100`, `1k`, `max` |\n| `-batch`       | `0`       | Max half-cycles per UI tick (0 = auto-tune at startup)|\n| `-cpuprofile`  | (off)     | Write CPU pprof to file                               |\n| `-memprofile`  | (off)     | Write heap pprof at exit                              |\n\nThe wasm build doesn't take flags; it boots with the same defaults.\nUser-facing controls live in the menus and keyboard shortcuts.\n\n## Memory map\n\nHardware-realistic address decoding — components claim their ranges\nexactly the way a 74HC138 chip-select decoder would on a real board.\nA two-stage decoder (A13–A15 → 8 KB regions; A8–A11 within the I/O\nregion → 256 B sub-regions) gives every peripheral its own CS line\nwith no chip-select collisions.\n\n| Range              | Component                  | Size    |\n|--------------------|----------------------------|---------|\n| `$0000`–`$1FFF`    | RAM                        | 8 KB    |\n| `$A000`–`$A3FF`    | VIC color plane            | 1 KB CS (520 B used) |\n| `$A400`–`$A7FF`    | VIC char plane             | 1 KB CS (520 B used) |\n| `$A800`–`$ABFF`    | VIC controller             | 1 KB CS (16 B used)  |\n| `$B000`–`$B0FF`    | 6522 VIA #1                | 256 B CS (regs mirror ×16) |\n| `$B100`–`$BFFF`    | peripheral slots (15 ×)    | 256 B CS each |\n| `$C000`–`$DFFF`    | VIC graphics plane         | 8 KB (160 × 100 @ 4bpp) |\n| `$E000`–`$FFFF`    | ROM (reset vector at `$FFFC`) | 8 KB |\n\nVIC controller registers (offsets within `$A800`):\n\n| Off  | Reg          | Behavior                                          |\n|------|--------------|---------------------------------------------------|\n| `+0` | Cmd          | Write triggers an op (Clear, Shift\\*, Rot\\*, Invert, Rect\\*, Gfx\\*) |\n| `+1` | Pause        | `1` = UI shows snapshot; `0` = UI shows live memory |\n| `+2` | Frame        | Any write captures a new snapshot (use while paused) |\n| `+3` | RectX        | Rect parameters consumed by `CmdRect*` and `CmdGfx*` |\n| `+4` | RectY        | opcodes — clamped to display bounds                |\n| `+5` | RectW        |                                                   |\n| `+6` | RectH        |                                                   |\n| `+7` | GfxColor     | Current draw color for `CmdGfx*` (palette idx 0–15) |\n| `+8` | Mode         | `0` = char (default), `1` = graphics              |\n\nVIA #1 — Phase 1 implements **Timer 1** in free-running and one-shot\nmodes plus IFR/IER semantics; ports, T2, SR, and PCR are stubbed and\nread/write a backing byte without side effects yet. The chip is\nclocked from its own 1 MHz oscillator (independent of the CPU), so\ndemos that pace off T1 keep ticking even while the CPU is single-\nstepping or paused — same as a real 65C22S board with a separate\ntimer crystal. Pacing pattern (canonical W65C22):\n\n```asm\n; Set up T1 free-run with latch = $C350 (~50 ms @ 1 MHz)\nLDA #$50  : STA $B006   ; T1L-L\nLDA #$C3  : STA $B005   ; T1C-H — copies latch→counter, starts T1\nLDA #$40  : STA $B00B   ; ACR bit 6 = T1 free-run\n\n; Poll for underflow\nWAIT: LDA $B00D         ; IFR\n      AND #$40          ; T1 flag\n      BEQ WAIT\n      LDA $B004         ; T1C-L read clears IFR T1\n```\n\n## CPU backends\n\n| Backend  | Speed       | What it is                                            |\n|----------|-------------|-------------------------------------------------------|\n| `interp` | several MHz | Conventional 151-opcode interpretive 6502 (default)   |\n| `netsim` | ~26 kHz     | Transistor-level [Visual6502](https://github.com/trebonian/visual6502) port — every cycle simulates ~3500 transistors |\n| `remote` | wire-bound  | The CPU lives in another process — a browser tab, an FPGA on the LAN, a Pi across the room — dialed in over a WebSocket. The TUI keeps the bus, RAM, ROM, and VIA local; every cycle round-trips for memory access |\n\nThe `Backend` interface (`cpu/backend.go`) lets you swap at runtime\nvia the **CPU** menu. All three expose the same address/data bus\nstate plus IRQ/NMI for the simulator's introspection windows.\n\n### Remote CPU — watch the silicon think in a browser tab\n\nStart the TUI with `-cpu=remote` and it boots into \"waiting\" mode\nwith no CPU. The terminal binds an HTTP listener (`-remote-addr\n:7777` by default) that serves both the `/cpu` WebSocket endpoint\n*and* a self-hosted browser page at `/`:\n\n```sh\n./bin/6502-sim -cpu=remote\n# then open http://localhost:7777/ in your browser\n```\n\nThe page boots a foxpro-go shell containing the transistor-level\n`netsim` core wired to a [Visual6502](https://github.com/trebonian/visual6502)-style\nlive die rendering. As soon as the page connects, the TUI's CPU\nwindow stops saying \"waiting\" and the demo starts running — every\nhalf-cycle round-trips between the terminal (which owns RAM, ROM,\nVIA timers, and the framebuffer) and the browser (which owns the\nCPU). The chip lights up node-by-node as instructions execute, with\nthe TUI showing the same activity on the bus side.\n\nIt's not fast — roughly 400 Hz on a localhost loop, slower over a\nLAN — but that's the point. You can read it. Close the browser tab\nand the TUI auto-pauses; open it again and it auto-resumes from\nreset.\n\nSame protocol works for any client that speaks the wire\n(`cpu/remote/proto.go`): there's a Go-only reference at\n`cmd/6502-cpu-fake/` for smoke testing, and the door is open for an\nFPGA-hosted real 6502 driving a TUI over TCP.\n\n## Windows\n\nEvery component gets its own floating, draggable window. Click in the\ntitle bar to drag, click the corner to resize.\n\n- **CPU** — A/X/Y/S/PC, P flags, half-cycle counter, live address bus,\n  data bus, R/W direction, IRQ/NMI line states.\n- **RAM** / **ROM** (Memory views) — hex view + ASCII column with\n  editable base address (click the `$XXXX:` button, type 4 hex\n  digits). Trace tinting: yellow = write that *changed* the byte,\n  brown = write that left it unchanged, green = read. `v` cycles\n  Hex / Disasm / Labels — Labels shows declared symbols within the\n  current region (or a per-byte fallback view for regions without\n  symbols). The disasm column substitutes operand addresses with\n  symbol names where known and appends per-instruction comments.\n- **VIC / Video** — 40 × 13 framebuffer with 16-color palette, plus a\n  160 × 100 graphics plane (when in graphics mode). Right column has\n  buttons for every controller command. Below the framebuffer, a\n  scrollable hex strip shows the VIC's controller region.\n- **VIA 1** — live snapshot of the chip's state: ports + DDRs at the\n  top, then Timer 1 (counter / latch / mode / armed flag), then ACR\n  decoded + IFR + IER bit dots (● set, . clear). The chip's base\n  address + crystal speed live in the title bar. The counter ticks\n  down even when the CPU is paused or stepping, because the VIA's\n  crystal runs independently.\n- **Monitor** — the shared REPL described above. Toggleable from\n  the Window menu in the terminal build; visible on startup in the\n  browser build. Common pane across all three apps.\n- **Logic Analyzer** (scope) — hidden by default; toggleable. 256\n  cycles of bus-trace history with auto-tuned sampling stride.\n\nRun/Stop/Step + speed controls live on the menu bar's right-side\ntray (clickable). The Clock window was removed when the bridge\nlanded — every action is in the menu, keyboard hotkeys, or the\nMonitor's command line.\n\n## Demos\n\nSelectable from the **Demo** menu, in three sections:\n\n| Demo                | What it does                                            |\n|---------------------|---------------------------------------------------------|\n| Marquee             | Scrolling \"HELLO 6502 SIM\"; paces via VIA T1 (default boot demo for TUI) |\n| Bouncer             | Single `*` bouncing across row 6                       |\n| Scroller            | Diagonal gradient scrolling up the display              |\n| Snow (LFSR)         | 8-bit Galois LFSR fills + clears the framebuffer       |\n| Scroller (framed)   | Same as Scroller but Pause + Frame for clean snapshots |\n| Blitter (RAM→VIC)   | Copies byte patterns out of RAM into the VIC planes    |\n| Quadrants           | 4 independent rect rotations using `CmdRect*`          |\n| Bouncing Balls      | Four colored balls in graphics mode, paced via VIA T1 (wasm only — TUI has no graphics plane) |\n\nAll demos are built via the in-tree `asm` package — a small fluent\n6502 assembler that emits bytes plus per-instruction comments and\nnamed memory symbols, surfaced by the Memory window's Labels and\nDisasm views.\n\n## Menu shortcuts\n\n| Key       | Action                              |\n|-----------|-------------------------------------|\n| `Z`       | Reset machine (does NOT stop the clock — like a hardware reset button) |\n| `F2`      | Toggle command window               |\n| `R`       | Run                                 |\n| `.`       | Stop                                |\n| `S`       | Step one instruction (until PC changes) |\n| `T`       | Step one half-cycle (\"tick\")        |\n| `Esc`     | Quit (terminal) · close menu (browser, where Quit is disabled) |\n\nIn the Memory window:\n\n| Key       | Action                              |\n|-----------|-------------------------------------|\n| `g`       | Edit base address                   |\n| `v`       | Cycle view: Hex / Disasm / Labels   |\n| `i`       | Toggle disassembly info panel       |\n\nIn the VIC window's hex strip:\n\n| Key / mouse        | Action                      |\n|--------------------|-----------------------------|\n| Mouse wheel        | Scroll memBase by 1 row     |\n| `[` / `]`          | Scroll by 1 row (16 bytes)  |\n| `{` / `}`          | Scroll by 1 page (112 bytes) |\n| Click `▲` / `▼`    | ±1 row                      |\n| Click track        | Page up/down                |\n| Drag `◆`           | Jump to position            |\n\n## Architecture\n\nThe execution model has two goroutines: the **foxpro UI thread**\n(handles input, draws windows) and the **Hub Pump** (drives the CPU\n+ peripherals in slices, synchronously). They serialise through a\nsingle mutex — concurrent reads from the UI side take a query lock;\nthe Pump holds it during each slice. Same model native + wasm.\nIn wasm, the Pump yields to the JS event loop every ~10 ms in Max\nmode so the browser tab can render.\n\nThe Pump slices each \"tick\" into 200-half-cycle chunks and pairs\neach `RunUntil` with a `bus.Tick(virtualDt)` for peripherals — so\npolling-based demos (those that LDA/AND/BEQ a peripheral flag in a\ntight wait loop) observe timer underflows multiple times per app\nframe instead of just once. The driver auto-tunes per-tick batch\nsize at startup to fit the host's tick budget.\n\nComponents self-describe their register layouts via the optional\n`bus.Labeller` interface (`Symbols() []asm.Symbol`), so the Memory\nwindow's Labels view annotates the VIC and VIA register regions\nautomatically — no hand-maintained mapping. Time-driven peripherals\nimplement `bus.Ticker` and get fanned out automatically.\n\nThe **bridge protocol** is a separate layer above the Hub. Clients\n(remote `cmd/6502-control`, in-process Monitor in `cmd/6502-sim` /\n`cmd/6502-wasm`, future MCP / VS Code) implement / consume the\n`bridge.Target` interface; the transport (TCP NDJSON or direct Go\ncalls via `bridge.HubDirect`) is the only thing that differs.\n\nRead `docs/architecture.md` for layering + component contracts,\n`docs/bridge-v2.md` for the protocol surface, and `docs/roadmap.md`\nfor remaining work.\n\n## Project layout\n\n```\ncmd/6502-sim/         terminal entry — main wiring, flags, profiling\ncmd/6502-sim-serve/   headless bridge server (no UI, listens on :6502)\ncmd/6502-control/     remote controller TUI — bridge client over NDJSON/TCP\ncmd/6502-wasm/        browser entry — wasm-tagged, uses foxpro-go's wasm bridge\nasm/                  fluent 6502 assembler used by demos\nbackplane/            machine bus + interrupt aggregation + reset capability\nbridge/               protocol layer — Hub + Pump + Target interface + HubDirect\nclock/                Driver, Speeds, halfStep accumulator\ncpu/                  Backend interface + PCSetter capability\ncpu/netsim/           netsim adapter\ncpu/interp/           interpretive 151-opcode 6502 (with IRQ/NMI service paths)\ncomponents/           ram, rom, display, via\ndisasm/               151-opcode disassembler with cycle counts and effects\ninstrument/           Instrument facade — wraps backplane + driver\ninternal/bridgeclient/ Go wire client for the bridge protocol\ninternal/monitor/     shared Monitor REPL — drives any bridge.Target\ninternal/demos/       shared demo programs (text + graphics)\nui/                   cpuwin, ramwin, displaywin, viawin, scopewin, clockwin\nweb/                  static frontend served by the wasm build (built artifacts)\ndocs/                 architecture, bridge protocol, roadmap, systems\n```\n\n## Status\n\nWorking on both terminal and browser. The transistor-level core hits\n~26 kHz on a recent Mac; the interpretive core is several MHz. Both\npass the same demos.\n\nThe simulator is set up so each peripheral lives on its own\nchip-select region with realistic mirroring (the 6522's 16 registers\nmirror through a 256-byte CS block, exactly as on a real board with\nonly RS0–RS3 hooked up). Demos written here should run on real\nsilicon without modification.\n\n## Credits\n\nThe transistor-level CPU backend (`netsim`) and the live die view\n(`ui/visualcpuwin`) are built on data from\n[Visual6502](https://github.com/trebonian/visual6502) by **Greg James,\nBrian Silverman, and Barry Silverman** — the segment-definition polygon\ntable, node IDs, and layer color palette all come from that project.\nThe Visual6502 work is licensed under\n[CC BY-NC-SA 3.0](http://creativecommons.org/licenses/by-nc-sa/3.0/);\nsee [NOTICES](NOTICES) for the redistribution details.\n\n## License\n\nMIT — see [LICENSE](LICENSE).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcarledwards%2Fgo6sim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcarledwards%2Fgo6sim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcarledwards%2Fgo6sim/lists"}