{"id":17835048,"url":"https://github.com/carlosedp/chisel-template","last_synced_at":"2025-03-19T14:31:39.115Z","repository":{"id":141423191,"uuid":"380355367","full_name":"carlosedp/chisel-template","owner":"carlosedp","description":"Chisel HDL Template Repository","archived":false,"fork":false,"pushed_at":"2023-02-11T17:18:55.000Z","size":54,"stargazers_count":7,"open_issues_count":0,"forks_count":1,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-03-17T08:21:23.419Z","etag":null,"topics":["chisel","fpga","hardware","hdl","scala"],"latest_commit_sha":null,"homepage":"","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/carlosedp.png","metadata":{"files":{"readme":"Readme.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-06-25T21:15:11.000Z","updated_at":"2024-10-24T06:55:52.000Z","dependencies_parsed_at":null,"dependency_job_id":"02e5916e-7942-42fd-912f-a235acfb938c","html_url":"https://github.com/carlosedp/chisel-template","commit_stats":null,"previous_names":[],"tags_count":0,"template":true,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carlosedp%2Fchisel-template","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carlosedp%2Fchisel-template/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carlosedp%2Fchisel-template/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carlosedp%2Fchisel-template/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/carlosedp","download_url":"https://codeload.github.com/carlosedp/chisel-template/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":244444712,"owners_count":20453780,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel","fpga","hardware","hdl","scala"],"created_at":"2024-10-27T20:16:20.635Z","updated_at":"2025-03-19T14:31:39.108Z","avatar_url":"https://github.com/carlosedp.png","language":"Scala","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Chisel Template\n\n[![Scala CI](https://github.com/carlosedp/chisel-template/actions/workflows/scala.yml/badge.svg)](https://github.com/carlosedp/chisel-template/actions/workflows/scala.yml)\n\nThis is template project to demonstrate [Chisel](https://www.chisel-lang.org/) functionality with build scripts and tooling. The build is handled by Scala [mill](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html) with some make targets for ease-of-use.\n\nThe project includes a simple module (to be replaced with your design) and also have a test spec written with the [scalatest](https://www.scalatest.org/) and [chiseltest](https://github.com/ucb-bar/chiseltest) frameworks. The repository also have a GitHub Action to run automated tests on main branch and PRs.\n\nChisel Learning Resources:\n\n- [Chisel Book](https://github.com/schoeberl/chisel-book)\n- [Chisel Documentation](https://www.chisel-lang.org/chisel3/)\n- [Chisel API](https://www.chisel-lang.org/api/latest/chisel3/index.html)\n\nSoftware requirements:\n\n- Java JDK (\u003chttps://adoptium.net/installation/\u003e) - Mandatory\n- Gnu Make to run the generation targets\n- Verilator (as an option for simulation) - Optional\n- GTKWave (to visualize VCD files) - Optional\n\n## Generating Verilog\n\nVerilog code can be generated from Chisel by using the `chisel` Makefile target.\n\n```sh\nmake chisel\n```\n\nThe output verilog files are generated in the `./generated` directory.\n\nRunning tests can be done with:\n\n```sh\nmake test\n```\n\nMore targets can be listed by running `make`.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcarlosedp%2Fchisel-template","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcarlosedp%2Fchisel-template","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcarlosedp%2Fchisel-template/lists"}