{"id":17834999,"url":"https://github.com/carlosedp/chiselv","last_synced_at":"2025-08-16T01:33:04.210Z","repository":{"id":40296305,"uuid":"411039788","full_name":"carlosedp/chiselv","owner":"carlosedp","description":"A RISC-V Core (RV32I) written in Chisel HDL","archived":false,"fork":false,"pushed_at":"2024-06-12T18:49:41.000Z","size":499,"stargazers_count":97,"open_issues_count":4,"forks_count":17,"subscribers_count":6,"default_branch":"main","last_synced_at":"2024-12-08T08:04:18.159Z","etag":null,"topics":["chisel","core","fpga","risc-v","riscv"],"latest_commit_sha":null,"homepage":"","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/carlosedp.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":".github/FUNDING.yml","license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null},"funding":{"github":"carlosedp","patreon":"carlosedp"}},"created_at":"2021-09-27T20:53:51.000Z","updated_at":"2024-11-10T05:19:32.000Z","dependencies_parsed_at":"2024-06-13T01:47:35.643Z","dependency_job_id":"21fa9a49-f5f5-42a6-b353-e634b23b834f","html_url":"https://github.com/carlosedp/chiselv","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carlosedp%2Fchiselv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carlosedp%2Fchiselv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carlosedp%2Fchiselv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/carlosedp%2Fchiselv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/carlosedp","download_url":"https://codeload.github.com/carlosedp/chiselv/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":229992600,"owners_count":18156325,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chisel","core","fpga","risc-v","riscv"],"created_at":"2024-10-27T20:16:09.383Z","updated_at":"2024-12-16T16:30:08.990Z","avatar_url":"https://github.com/carlosedp.png","language":"Scala","funding_links":["https://github.com/sponsors/carlosedp","https://patreon.com/carlosedp"],"categories":[],"sub_categories":[],"readme":"# ChiselV - A RISC-V Processor in Chisel\n\n```plain\n(..,,***)\n ( #,,****)             MM''''''YMM dP       oo                   dP M''MMMMM''M\n  (,,.,,***)            M' .mmm. 'M 88                            88 M  MMMMM  M\n   (,,,,,,*,,)          M  MMMMMooM 88d888b. dP .d8888b. .d8888b. 88 M  MMMMP  M\n     (,,,,,,,,,)        M  MMMMMMMM 88'  '88 88 Y8ooooo. 88ooood8 88 M  MMMM' .M\n       ( .,,...,*)      M. 'MMM' .M 88    88 88       88 88.  ... 88 M  MMP' .MM\n         ( .,,,.., )    MM.     .dM dP    dP dP '88888P' '88888P' dP M     .dMMM\n           (,,.,,.,..)  MMMMMMMMMMM                                  MMMMMMMMMMM\n             (,*,.   ,)\n               (,*#/#.,)            INSTRUCTION SETS WANT TO BE FREE\n                  ,###.\n                    *#*(,\n                      /((((((((##.\n                    ...*(((((/(/(/##(\n                    .... ((((((((((###\n                      *....,(((((((((((###\n                        .,....(((((((((((###\n                          *....(/((((((((####/\n                            *.,,.,((((((((((((((\n                              /.,,,,((#((/(/***\n                                /...((((***\n                                  ,(*/*\n```\n\n[![Scala CI](https://github.com/carlosedp/chiselv/actions/workflows/scala.yml/badge.svg)](https://github.com/carlosedp/chiselv/actions/workflows/scala.yml)\n[![Scala Steward badge](https://img.shields.io/badge/Scala_Steward-helping-green.svg?style=flat\u0026logo=data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAA4AAAAQCAMAAAARSr4IAAAAVFBMVEUAAACHjojlOy5NWlrKzcYRKjGFjIbp293YycuLa3pYY2LSqql4f3pCUFTgSjNodYRmcXUsPD/NTTbjRS+2jomhgnzNc223cGvZS0HaSD0XLjbaSjElhIr+AAAAAXRSTlMAQObYZgAAAHlJREFUCNdNyosOwyAIhWHAQS1Vt7a77/3fcxxdmv0xwmckutAR1nkm4ggbyEcg/wWmlGLDAA3oL50xi6fk5ffZ3E2E3QfZDCcCN2YtbEWZt+Drc6u6rlqv7Uk0LdKqqr5rk2UCRXOk0vmQKGfc94nOJyQjouF9H/wCc9gECEYfONoAAAAASUVORK5CYII=)](https://scala-steward.org)\n\n\nThis project is a learning exercise for digital design, writing a RISC-V core and also\nhave a deeper understanding of [Chisel](https://www.chisel-lang.org/), an HDL language based on Scala.\n\nCurrently the target builds a RV32I core.\n\n## Generating Verilog\n\nVerilog code can be generated from Chisel sources by using the `chisel` Makefile target. If a `BOARD` parameter is passed, the target board PLL is included in the design. If it's not provided, a bypass PLL will be used.\n\n```sh\nmake chisel BOARD=artya7-35t\n```\n\nThe `BOARD` argument must match one of the `pll_BOARD.v` files in `/src/main/resources` directory.\n\nThe core can be simulated in Verilator using the commands:\n\n```sh\nmake verilator   # this will build the SOC, generate the Verilog files and Verilator project\nmake verirun     # This will copy the UART demo (RAM/ROM) binaries from gcc/helloUART and run Verilator\n```\n\nThe demo application can be adjusted in the Makefile to point to the dir and files for ROM and RAM.\n\n## Building for FPGAs\n\nThe standard build process uses locally installed tools like Java (for Chisel generation), Firtool, Yosys, NextPNR, Vivado and others. It's recommended to use [Fusesoc](https://github.com/olofk/fusesoc) for building the complete workflow by using containers thru a command launcher. In this case, the FPGA tools doesn't need to be installed locally.\n\n- Install a Java JDK for example from \u003chttps://adoptium.net/\u003e.\n- Install the latest Firtool, the SystemVerilog generator **into your path** from \u003chttps://github.com/llvm/circt/releases\u003e or using the `download_firtool.sh` script.\n- Install an FPGA programming tool like [OpenOCD](https://openocd.org/) or [openfpgaloader](https://github.com/trabucayre/openFPGALoader/).\n- Install Fusesoc with instructions below.\n\n### Fusesoc build and generation\n\nTo install Fusesoc (requires Python3 and pip):\n\n```sh\npip install --upgrade fusesoc\n```\n\n**Workaround that allows building for Xilinx A7 FPGAs with open-source tooling**\n\n\u003e After installing fusesoc, replace Edalize (one of it's components) with the one from my repository which contains a workaround that allows passing defines to Yosys, the synthesis tool\n\u003e `pip uninstall edalize`\n\u003e `pip install pip install git+https://github.com/carlosedp/edalize.git@symbiflow_defines`\n\u003e This happens because a recent change in Chisel/Firtool required the `ENABLE_INITIAL_MEM_=True` define to initialize the memories with code from a file (readmemh).\n\nCheck if it's working:\n\n```sh\n$ fusesoc --version\n1.12.0\n```\n\nIf the terminal reports an error about the command not being found check that the directory `~/.local/bin` is in your command search path (`export PATH=~/.local/bin:$PATH`).\n\nFusesoc allows multiple boards from different vendors to be supported by the project. It uses chisel-generator to generate Verilog from Scala sources and calls the correct board EDA backend to create it's project files.\n\nFor example, to generate the programming files for the **ULX3s** board based on Lattice ECP5:\n\n```sh\nmkdir fusesoc-chiselv \u0026\u0026 cd fusesoc-chiselv\n\n# Add requires fusesoc generators and the core\nfusesoc library add chiselv https://github.com/carlosedp/chiselv\nfusesoc library add fg https://github.com/fusesoc/fusesoc-generators\n\n# Download the command wrapper\nwget https://gist.github.com/carlosedp/c0e29d55e48309a48961f2e3939acfe9/raw/463951d3c826c8c9ffdb0173d52a74968d0ae6f7/runme.py\nchmod +x runme.py\n\n# Run fusesoc with the wrapper as an environment var\nEDALIZE_LAUNCHER=$(realpath ./runme.py) fusesoc run --target=ulx3s_85 carlosedp:chiselv:singlecycle\n\n# The output files will be on the local ./build dir:\n...\n# Output bitstream will be on build/carlosedp_demo_chiselblinky_0/ulx3s_85-trellis\n❯ ll build/carlosedp_chiselv_singlecycle_0/ulx3s_85-trellis\ntotal 6.9M\n-rw-r--r-- 1 cdepaula staff 1.2K Oct 15 16:25 proginfo.py\n-rw-r--r-- 1 cdepaula staff  507 Oct 15 16:25 boardconfig.yaml\n-rw-r--r-- 1 cdepaula staff  198 Oct 15 16:25 progload.mem\n-rw-r--r-- 1 cdepaula staff 1.6K Oct 15 16:25 carlosedp_chiselv_singlecycle_0.eda.yml\n-rw-r--r-- 1 cdepaula staff  483 Oct 15 16:25 edalize_yosys_procs.tcl\n-rw-r--r-- 1 cdepaula staff  247 Oct 15 16:25 edalize_yosys_template.tcl\n-rw-r--r-- 1 cdepaula staff 1.1K Oct 15 16:25 Makefile\n-rw-r--r-- 1 cdepaula staff  67K Oct 15 16:25 carlosedp_chiselv_singlecycle_0.blif\n-rw-r--r-- 1 cdepaula staff 708K Oct 15 16:25 carlosedp_chiselv_singlecycle_0.json\n-rw-r--r-- 1 cdepaula staff  57K Oct 15 16:25 carlosedp_chiselv_singlecycle_0.edif\n-rw-r--r-- 1 cdepaula staff  74K Oct 15 16:25 yosys.log\n-rw-r--r-- 1 cdepaula staff  32K Oct 15 16:25 carlosedp_chiselv_singlecycle_0.config\n-rw-r--r-- 1 cdepaula staff 9.8K Oct 15 16:25 next.log\n-rw-r--r-- 1 cdepaula staff 1.9M Oct 15 16:26 carlosedp_chiselv_singlecycle_0.bit\n-rw-r--r-- 1 cdepaula staff 3.9M Oct 15 16:26 carlosedp_chiselv_singlecycle_0.svf\n\n# Programming instructions will be printed-out.\n```\n\nJust program it to your FPGA with `OpenOCD` or [`openfpgaloader`](https://github.com/trabucayre/openFPGALoader) using printed instructions.\n\n\n## Planned features\n\n- Add a standard bus like Wishbone\n- Integrate peripherals thru this bus (UART, etc)\n- Add memory controller for SDRAM or DDR\n\n## Adding support to new boards\n\n\u003cdetails\u003e\n  \u003csummary\u003eClick to expand\u003c/summary\u003e\n\nSupport for new boards can be added in the `chiselv.core` file and programming instructions in the `proginfo/buildconfig.yaml` together with a board template text.\n\nThree sections are required:\n\n### Fileset\n\nFilesets lists the dependency from the chisel-generator, that outputs Verilog from Chisel (Scala) code. It also contains the static files used for each board like constraints and programming config that must be copied to the output project dir and used by EDA. The programming info text template is also added.\n\n```yaml\n  ulx3s-85:\n    depend: [\"fusesoc:utils:generators:0.1.6\"]\n    files:\n      - constraints/ecp5-ulx3s.lpf: { file_type: LPF }\n      - openocd/ft231x.cfg: { file_type: user }\n      - openocd/LFE5U-85F.cfg: { file_type: user }\n      - proginfo/ulx3s-template.txt: { file_type: user }\n```\n\n### Generate\n\nThe generator section contains the Chisel generator parameters. It has the arguments to be passed to Chisel (the board), the project name and the output files created by the generator to be used by the EDA.\n\n```yaml\n  ulx3s:\n    generator: chisel\n    parameters:\n      extraargs: \"--target:fpga -board ulx3s\"\n      buildtool: sbt\n      copy_core: true\n      output:\n        files:\n          - generated/Toplevel.v: { file_type: verilogSource }\n          - generated/GPIOInOut.v: { file_type: verilogSource }\n          - generated/pll_ulx3s.v: { file_type: verilogSource }\n```\n\n### Target\n\nFinally the target section has the board information to be passed to the EDA tools. Parameters like the package/die or extra parameters to synthesis or PnR. This is highly dependent of the EDA backend. It's name is the one passed on the `--target=` param on FuseSoc. It also references the fileset and generate configs.\n\n```yaml\n  ulx3s_85:\n    default_tool: trellis\n    description: ULX3S 85k version\n    filesets: [ulx3s-85, proginfo, progload]\n    generate: [ulx3s]\n    hooks:\n      post_run: [ulx3s-85f]\n    tools:\n      diamond:\n        part: LFE5U-85F-6BG381C\n      trellis:\n        nextpnr_options: [--package, CABGA381, --85k]\n        yosys_synth_options: [-abc9, -nowidelut]\n    toplevel: Toplevel\n```\n\n### Post-run script\n\nIf you desire to add a programming information text output after generating the bitstream files, add the board to the `scripts` section (and to it's target hooks) calling the proginfo.py with a board identifier that must match the `boardconfig.yaml` file in the `proginfo` dir.\n\n```yaml\n  ulx3s-85f:\n    cmd : [python3, proginfo.py, ulx3s-85f]\n```\n\nThe `boardconfig.yaml` file must contain the files names used by each board and a corresponding template `.txt` file that will contain the output text. This will be printed after bitstream generation.\n\n\u003c/details\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcarlosedp%2Fchiselv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcarlosedp%2Fchiselv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcarlosedp%2Fchiselv/lists"}