{"id":29356920,"url":"https://github.com/cesnet/ndk-fpga","last_synced_at":"2026-02-05T04:33:23.648Z","repository":{"id":37577095,"uuid":"481198706","full_name":"CESNET/ndk-fpga","owner":"CESNET","description":"Network Development Kit (NDK) for FPGA cards with example application","archived":false,"fork":false,"pushed_at":"2026-01-27T07:22:12.000Z","size":70062,"stargazers_count":68,"open_issues_count":2,"forks_count":12,"subscribers_count":7,"default_branch":"devel","last_synced_at":"2026-01-27T20:21:36.043Z","etag":null,"topics":["ethernet","fpga","liberouter","network-development-kit","vhdl"],"latest_commit_sha":null,"homepage":"https://www.liberouter.org/ndk/","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/CESNET.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2022-04-13T12:01:22.000Z","updated_at":"2026-01-27T07:21:32.000Z","dependencies_parsed_at":"2024-02-09T10:41:01.251Z","dependency_job_id":"cb2f8e29-bc72-4945-8d87-9481a6c2725c","html_url":"https://github.com/CESNET/ndk-fpga","commit_stats":null,"previous_names":["cesnet/ndk-fpga"],"tags_count":18,"template":false,"template_full_name":null,"purl":"pkg:github/CESNET/ndk-fpga","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CESNET%2Fndk-fpga","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CESNET%2Fndk-fpga/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CESNET%2Fndk-fpga/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CESNET%2Fndk-fpga/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/CESNET","download_url":"https://codeload.github.com/CESNET/ndk-fpga/tar.gz/refs/heads/devel","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CESNET%2Fndk-fpga/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29111892,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-05T03:44:17.043Z","status":"ssl_error","status_checked_at":"2026-02-05T03:44:12.077Z","response_time":65,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["ethernet","fpga","liberouter","network-development-kit","vhdl"],"created_at":"2025-07-09T05:40:57.211Z","updated_at":"2026-02-05T04:33:23.641Z","avatar_url":"https://github.com/CESNET.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# NDK-FPGA\n\nThis repository contains FPGA part of the Network Development Kit (NDK) for FPGA acceleration cards. The NDK allows users to quickly and easily develop FPGA-accelerated network applications. The NDK is optimized for high throughput and scalability to support up to 400 Gigabit Ethernet. The NDK-based Minimal (reference) application is also included in this (NDK-FPGA) repository.\n\nThe NDK-based Minimal application is a simple example of how to build an FPGA application using the NDK. It can also be a starting point for your NDK-based application. The NDK-based Minimal application does not process network packets in any way; it only sends and receives them. If the DMA IP is enabled, then it forwards the network packets to the computer memory. You can find more detailed information in [the NDK-FPGA documentation (devel branch) here](https://cesnet.github.io/ndk-fpga/devel/).\n\n**Please note that some integrated IP (e.g. DMA Medusa IP) are not part of the open-source NDK-FPGA. These IPs can only be obtained through our partners, [see the section Partners](#partners).**\n\n## How to start\n\nBefore you get started, there are a few requirements that you need to have.\n\n### Requirements and supported FPGA cards\n\n- To build the FPGA firmware, you must have installed the **Intel Quartus Prime Pro 25.1** or **Xilinx Vivado 2022.2** (depending on the target card), including a valid license.\n- We recommend using the **Questa Sim-64 2025.2** tool to run HDL verifications (UVM).\n- To control an FPGA card with an application based on the NDK framework, you also need:\n    - [NDK Linux driver and SW tools](https://github.com/CESNET/ndk-sw)\n- Supported FPGA cards in the NDK framework available as open-source:\n    - ReflexCES XpressSX AGI-FH400G card (BOARD_REV = 0 or 1 requires Quartus version 22.4)\n    - Intel Stratix 10 DX FPGA Development Kit (DK-DEV-1SDX-P)\n    - Silicom fb4CGg3@VU9P card (also in variant fb2CGg3@VU9P)\n    - Silicom fb2CGhh@KU15P card\n    - Silicom fb2CDg1@AGM39D-2 (ThunderFjord) card (preliminary support).\n    - Silicom N5014 card\n    - Silicom N6010 card\n    - Bittware IA-420f card\n    - Bittware IA-440i card\n    - AMD/Xilinx Alveo U200\n    - AMD/Xilinx Alveo U55C\n    - AMD/Xilinx Virtex UltraScale+ FPGA VCU118 Evaluation Kit\n    - PRO DESIGN FALCON Stratix 10 (only EXPERIMENTAL support)\n    - Terasic Mercury A2700 Accelerator Card\n    - iWave G35P Accelerator card\n    - Napatech NT200A02\n- Other supported FPGA cards in the NDK framework but not available as open-source:\n    - Netcope NFB-200G2QL card\n\n### How to clone the necessary repositories\n\nJust clone the NDK-FPGA repository from GitHub:\n\n```\ngit clone https://github.com/CESNET/ndk-fpga.git\n```\n\nCESNET developers who have access to closed-source repositories can use a single command to clone the repository, including its submodules (from private GitLab):\n```\ngit clone --recursive git@gitlab.liberouter.org:ndk/ndk-fpga.git\n```\n\n### Next steps\n\nThe [NDK-FPGA documentation (devel branch) in chapter \"How to start\"](https://cesnet.github.io/ndk-fpga/devel/ndk_core/doc/how_to_start.html) lists further steps for building the FPGA firmware, loading it into the FPGA card and also using it.\n\n## Documentation\n\nWe use a documentation system based on the [Sphinx tool](https://www.sphinx-doc.org), which compiles complete documentation from source files in the [reStructuredText](https://docutils.sourceforge.io/rst.html) format. We also use the [Sphinx-vhdl](https://github.com/CESNET/sphinx-vhdl) for generating documentation from the VHDL code. The documentation automatically builds with each contribution to the devel/release branch and is available online here:\n- [**NDK-FPGA documentation (release branch)**](https://cesnet.github.io/ndk-fpga/release/)\n- [**NDK-FPGA documentation (devel branch)**](https://cesnet.github.io/ndk-fpga/devel/)\n\n### How to manually build documentation\n\nFirst, you need to prepare the environment:\n```\n$ cd doc\n$ python3 -m venv venv-doc\n$ source venv-doc/bin/activate\n$ pip install -r requirements.txt\n```\n\nThen the documentation is generated simply by issuing this command:\n```\n$ make html\n```\n\nThe output is in the `doc/build/index.html` file.\n\n## Partners\n\n### DYNANIC (formerly BrnoLogic)\n\nThe NDK including the DMA Medusa IP and professional support is [available through our partner DYNANIC](https://dyna-nic.com/ndk-and-dma-engine/).\n\n## Related publications\n\n- J. Cabal, J. Sikora, Š. Friedl, M. Špinler and J. Kořenek, \"[FPL Demo: 400G FPGA Packet Capture Based on Network Development Kit](https://ieeexplore.ieee.org/document/10035175),\" 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL), Belfast, United Kingdom, 2022, pp. 474-474, doi: [10.1109/FPL57034.2022.00090](https://doi.org/10.1109/FPL57034.2022.00090).\n- J. Kubálek, J. Cabal, M. Špinler and R. Iša, \"[DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers](https://ieeexplore.ieee.org/document/9444087),\" *2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)*, 2021, pp. 258-258, doi: [10.1109/FCCM51124.2021.00045](https://doi.org/10.1109/FCCM51124.2021.00045).\n- L. Kekely, J. Cabal, V. Puš and J. Kořenek, \"[Multi Buses: Theory and Practical Considerations of Data Bus Width Scaling in FPGAs](https://ieeexplore.ieee.org/document/9217811),\" *2020 23rd Euromicro Conference on Digital System Design (DSD)*, 2020, pp. 49-56, doi: [10.1109/DSD51259.2020.00020](https://doi.org/10.1109/DSD51259.2020.00020).\n\n## License\n\nUnless otherwise noted, the content of this repository is available under the BSD 3-Clause License. Please read [LICENSE file](LICENSE).\n\n- See also the license information (in README.md) in each Git submodule.\n\n### Modules/files taken from other sources\n\n- [I2C Master controller](comp/ctrls/i2c_hw/) by Richard Herveille from [opencores.org](https://opencores.org/projects/i2c) in `comp/ctrls/i2c_hw` under something like a BSD license.\n- [SPI Master controller](comp/ctrls/spi/) by Jonny Doin from [opencores.org](https://opencores.org/projects/spi_master_slave) in `comp/ctrls/spi` under LGPL license.\n- The .ip files located in the `/comp/base/misc/adc_sensors/` folder were generated in Intel Quartus Prime Pro, and their use may be subject to additional license agreements.\n- The .ip file `comp/ctrls/sdm_client/mailbox_client.ip` was generated in Intel Quartus Prime Pro, and their use may be subject to additional license agreements.\n- The .ip files located in the `cards/\u003cVENDOR\u003e/\u003cCARD_NAME\u003e/src/ip/` folder were generated in the Intel Quartus Prime Pro, and their use may be subject to additional license agreements.\n- The .xci files located in the `cards/\u003cVENDOR\u003e/\u003cCARD_NAME\u003e/src/ip/` folder were generated in the Xilinx Vivado, and their use may be subject to additional license agreements.\n- The files located in the `cards/silicom/n6010/src/comp/pmci/pmci_ip` and `cards/silicom/n6010/scripts` folders were taken from the [ofs-agx7-pcie-attach repository](https://github.com/OFS/ofs-agx7-pcie-attach) and are subject to the MIT license. Please read [LICENSE.txt file](cards/silicom/n6010/scripts/LICENSE.txt).\n- The files located in the `cards/silicom/n5014/src/comp/hbm` folder were taken from the [ofs-fim-common repository](https://github.com/OFS/ofs-fim-common) and are subject to the MIT license. Please read [LICENSE.txt file](cards/silicom/n5014/src/comp/hbm/LICENSE.txt).\n- The files located in the `comp/base/hash/spookyhash/sw/` by Bob Jenkins from [burtleburtle.net](https://burtleburtle.net/bob/hash/spooky.html), Public domain.\n\n## Repository Maintainer\n\n- Jakub Cabal, cabal@cesnet.cz\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcesnet%2Fndk-fpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcesnet%2Fndk-fpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcesnet%2Fndk-fpga/lists"}