{"id":28089196,"url":"https://github.com/charank-glitch/rv32i","last_synced_at":"2025-05-13T12:54:44.915Z","repository":{"id":283934665,"uuid":"953335530","full_name":"CharanK-glitch/RV32I","owner":"CharanK-glitch","description":"Sapphire SoC: RV32I RISC-V core optimized for FPGAs, featuring UVM verification, AXI4-Lite bus, FreeRTOS support, and Shakti-inspired design. Open-source under MIT license for embedded/IoT applications.","archived":false,"fork":false,"pushed_at":"2025-05-02T15:37:25.000Z","size":215,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2025-05-02T16:36:37.561Z","etag":null,"topics":["assembly","c","python","riscv","rtos","rv32i","shell","soc","systemverilog","uvm-verification","verilog"],"latest_commit_sha":null,"homepage":"https://github.com/CharanK-glitch/RV32I","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/CharanK-glitch.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2025-03-23T05:36:18.000Z","updated_at":"2025-05-02T15:37:28.000Z","dependencies_parsed_at":"2025-03-23T06:37:16.796Z","dependency_job_id":null,"html_url":"https://github.com/CharanK-glitch/RV32I","commit_stats":null,"previous_names":["charank-glitch/rv32i"],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CharanK-glitch%2FRV32I","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CharanK-glitch%2FRV32I/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CharanK-glitch%2FRV32I/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CharanK-glitch%2FRV32I/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/CharanK-glitch","download_url":"https://codeload.github.com/CharanK-glitch/RV32I/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253948328,"owners_count":21988953,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembly","c","python","riscv","rtos","rv32i","shell","soc","systemverilog","uvm-verification","verilog"],"created_at":"2025-05-13T12:54:44.105Z","updated_at":"2025-05-13T12:54:44.904Z","avatar_url":"https://github.com/CharanK-glitch.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# I. RISC-V RV32I(single - Core) Architecture and Implementation\n\n1. Overview\n\nThe RV32I (RISC-V 32-bit Integer) architecture is a reduced instruction set computing (RISC) design that provides a minimal yet efficient foundation for processor development. It follows a load-store architecture, ensuring simple and predictable execution.\n\n2. Architecture \u0026 Pipelining\n\nRV32I follows a five-stage pipeline:\n\t1.\tInstruction Fetch (IF) – Retrieves instruction from memory.\n\t2.\tInstruction Decode (ID) – Decodes the opcode and operands.\n\t3.\tExecute (EX) – Performs ALU operations.\n\t4.\tMemory Access (MEM) – Reads/writes from/to memory.\n\t5.\tWrite-back (WB) – Stores results into registers.\n\nThis pipelined execution enhances parallelism but introduces hazards, which require handling through stalling, forwarding, and prediction mechanisms.\n\n3. Instruction Set \u0026 Extensions\n\nThe base RV32I set includes arithmetic, logical, branch, load/store, and control instructions. It can be extended with:\n\t•\tM (Multiplication/Division)\n\t•\tA (Atomic operations)\n\t•\tF/D (Floating-point)\n\t•\tC (Compressed instructions for reduced memory footprint)\n\t•\tZicsr \u0026 Zifencei (Control and memory ordering)\n\n4. Privileged \u0026 Unprivileged Modes\n\n\t•\tMachine Mode (M-mode): Highest privilege level, directly controls system resources.\n\t•\tUser Mode (U-mode): Executes application code with restricted access.\n\t•\tSupervisor Mode (S-mode) (optional): Handles OS-level management.\n\nPrivilege levels are managed via Control and Status Registers (CSRs).\n\n5. Data Paths \u0026 Hazard Handling\n\nThe datapath includes register files, ALU, control unit, memory access unit, and pipeline registers. Key challenges include:\n\t•\tData Hazards: Managed via forwarding or stalls.\n\t•\tControl Hazards: Mitigated through branch prediction and pipeline flushing.\n\t•\tStructural Hazards: Minimized by separating instruction and data memory or using multi-port registers.\n\n6. FreeRTOS Implementation\n\nThe architecture can be extended to run FreeRTOS, enabling real-time scheduling, task management, and interrupt handling. This requires integrating timer interrupts, system calls, and context switching in the RISC-V privilege model.\n\n7. Future Enhancements\n\n\t•\tAdvanced Branch Prediction: Implementing perceptron-based dynamic prediction for reduced stalls.\n\t•\tCache \u0026 Memory Hierarchy Optimization: Exploring L1/L2 caching for efficient memory access.\n\t•\tMulticore Support: Extending to RV64GC with multi-core synchronization.\n\nThis repository serves as a foundation for understanding and developing RISC-V-based embedded and OS-level implementations.\n\n\n![risc_architecture](https://github.com/user-attachments/assets/f0b33f83-b1b2-42e5-95cd-d2f98ebea5d6)\n\n\n# II. RTOS Implementation on RV32I Core\n\n## 1. Overview\nThis document describes the implementation of an **RTOS** on the **RV32I Core**, taking inspiration from **Steel** documentation. The integration includes task management, scheduling, interrupt handling, and peripheral interaction.\n\n## 2. System Architecture\n\n### 2.1 Components\n- RV32I Core: Custom RISC-V core with MMU (optional for RTOS)\n- cheduler: Preemptive round-robin or priority-based scheduling\n- **Task Management**: Context switching and multi-threading support\n- **Interrupt Handling**: External and software-triggered interrupts\n- **Memory Management**: Stack and heap allocation per task\n- **Synchronization**: Mutex, semaphores, and event flags\n- **Drivers**: UART, GPIO, Timer, and SPI/I2C\n\n### 2.2 RTOS Features\n| Feature | Implementation |\n|---------|---------------|\n| Task Switching | Context switch via software interrupts |\n| Scheduling | Preemptive Round-Robin / Priority-based |\n| Interrupts | RISC-V PLIC-based handling |\n| Timers | System tick using Machine Timer (MTIME) |\n| IPC | Message Queues, Semaphores |\n| Memory | Stack and Heap allocation per task |\n\n## 3. RTOS Integration with RV32I\n\n### 3.1 System Tick Timer (SysTick)\nThe system tick is configured using the **MTIME** register:\n```c\n#define MTIME       (*(volatile uint64_t*)0x200BFF8)\n#define MTIMECMP    (*(volatile uint64_t*)0x2004000)\n#define TIMER_FREQ  1000000\n\nvoid set_systick(uint64_t interval) {\n    MTIMECMP = MTIME + interval;\n}\n```\n\n### 3.2 Context Switching Mechanism\nThe RTOS requires **context switching** between tasks using the RISC-V `mret` instruction.\n```assembly\ncsrrw sp, mscratch, sp  // Save SP\ncsrrw ra, mepc, ra      // Save Return Address\ncsrw mscratch, sp       // Restore SP\nmret                    // Return from exception\n```\n\n### 3.3 Task Scheduler\nThe task scheduler handles multiple threads and enforces time-slicing.\n```c\nvoid scheduler() {\n    current_task = (current_task + 1) % NUM_TASKS;\n    context_switch(tasks[current_task]);\n}\n```\n\n### 3.4 Interrupt Handling\nAll peripherals trigger **software interrupts** managed by the **PLIC**:\n```c\nvoid external_interrupt_handler() {\n    uint32_t irq = PLIC_CLAIM;\n    if (irq == UART_IRQ) {\n        uart_handle_irq();\n    }\n    PLIC_COMPLETE = irq;\n}\n```\n\n## 4. Peripheral Drivers\n\n### 4.1 UART Driver\n```c\nvoid uart_init() {\n    UART_CTRL = ENABLE_TX | ENABLE_RX;\n}\n\nvoid uart_write(char c) {\n    while (!(UART_STATUS \u0026 TX_READY));\n    UART_DATA = c;\n}\n```\n\n### 4.2 GPIO Driver\n```c\nvoid gpio_write(uint32_t pin, uint8_t value) {\n    if (value)\n        GPIO_SET = (1 \u003c\u003c pin);\n    else\n        GPIO_CLEAR = (1 \u003c\u003c pin);\n}\n```\n\n## 5. Testing and Debugging\n- **Simulation**: Using **QEMU-RISCV** to test RTOS scheduling\n- **FPGA Deployment**: Running on **Artix-7**\n- **Debugging**: OpenOCD + GDB with RTOS-aware debugging\n\n## 6. Future Enhancements\n- Implement **Mutex and Semaphores** for real-time synchronization\n- Add **dynamic memory allocation** for flexible task management\n- Optimize **power management** for embedded applications\n- Port **FreeRTOS** for multi-threading support\n\n---\nThis document provides a roadmap for **RTOS integration on RV32I**, enabling **real-time task scheduling, peripheral control, and multi-threading** support.\n\n\n\n# III. RV Core Implementation on Sapphire SOC\n\n**Inspired by:** [SHAKTI Project](https://www.shakti.org.in/) | **Design Philosophy:** [RISC-V Steel](https://github.com/riscv-steel/riscv-steel)\n\n## Overview\nSapphire SoC is a minimalist RV32I RISC-V implementation targeting FPGA-based embedded systems. Designed with the simplicity-first approach of RISC-V Steel and the robustness of SHAKTI-class cores, it features:\n\n- 5-stage in-order pipeline\n- AXI4-Lite system bus\n- FPGA-optimized microarchitecture\n- FreeRTOS-compatible interrupt system\n\n\n![Screenshot 2025-03-23 213107](https://github.com/user-attachments/assets/1aa3e888-c468-46d0-88d6-d59ba2a0da30)\n\n\n\n## Features\n- **RV32I Compliance**: Full support for Base Integer ISA (v2.1)\n- **Pipeline**: IF-ID-EX-MEM-WB with hazard detection\n- **Memory**:\n  - 4KB ICache / 4KB DCache\n  - Memory-mapped peripherals (UART, GPIO, Timer)\n- **Interrupts**: PLIC with 32 priority levels\n- **FPGA Targets**:\n  - Genesys-2 (Xilinx Kintex-7)\n  - DE10-Nano (Intel Cyclone V)\n\n## Architecture\n### Core Pipeline\n```SystemVerilog\nmodule sapphire_core (\n  input  logic        clk,\n  input  logic        resetn,\n  // AXI4-Lite Interface\n  axi_lite_if.master  axi_bus,\n  // Interrupt Interface\n  input  logic [31:0] irq_lines\n);\n\n```\n\n### Memory Map\n| Address Range       | Description          |\n|---------------------|----------------------|\n| `0x0000_0000-0x0000_FFFF` | Boot ROM (64KB)    |\n| `0x2000_0000-0x2000_0FFF` | GPIO               |\n| `0x3000_0000-0x3000_00FF` | UART              |\n| `0x4000_0000-0x4FFF_FFFF` | AXI4-Lite Memory  |\n\n## Getting Started\n### Prerequisites\n- RISC-V GCC Toolchain\n- Verilator (v5.0+)\n- Vivado 2022.1 (FPGA builds)\n\n### Build \u0026 Simulate\n```bash\ngit clone https://github.com/yourusername/sapphire-soc\ncd sapphire-soc\n\n# Run UVM tests\nmake sim TEST=axi_smoke\n\n# Synthesize for Genesys-2\nmake fpga BOARD=genesys2\n```\n\n### Example: Hello World\n```c\n#include \"sapphire.h\"\n\nint main() {\n  uart_init(115200);\n  uart_puts(\"Sapphire SoC Booted!\\n\");\n  \n  while(1) {\n    led_toggle();\n    delay_ms(500);\n  }\n  return 0;\n}\n```\n\n## Performance\n| Metric              | Sapphire | SHAKTI C-Class | PicoRV32 |\n|---------------------|----------|----------------|----------|\n| ISA Support         | RV32I    | RV64IMAC       | RV32I    |\n| Pipeline Stages     | 5        | 3              | -        |\n| FPGA Freq (MHz)     | 75       | 100            | 150      |\n| LUT Utilization     | 1,200    | 2,500          | 750      |\n| Verification Method | UVM+FPGA | Formal         | Direct   |\n\n## Contributing\n1. Fork the repository\n2. Create feature branch (`git checkout -b feature/amazing-feature`)\n3. Commit changes (`git commit -m 'Add amazing feature'`)\n4. Push to branch (`git push origin feature/amazing-feature`)\n5. Open a Pull Request\n   \n\n## Acknowledgments\n- [SHAKTI Project](https://www.shakti.org.in/) for architectural inspiration\n- [RISC-V Steel](https://github.com/riscv-steel) for verification methodology\n- [Verilator](https://www.veripool.org/verilator/) simulation toolkit\n\n\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcharank-glitch%2Frv32i","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcharank-glitch%2Frv32i","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcharank-glitch%2Frv32i/lists"}