{"id":20195445,"url":"https://github.com/charkster/scarf","last_synced_at":"2026-05-27T23:32:33.953Z","repository":{"id":158988142,"uuid":"277021475","full_name":"charkster/SCARF","owner":"charkster","description":"SCARF - “Scarf Connects A Raspberry pi to Fpga”","archived":false,"fork":false,"pushed_at":"2022-10-22T23:15:16.000Z","size":902,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-10T08:48:33.132Z","etag":null,"topics":["fpga","fpga-designs","raspberry-pi","scarf","spi-slave"],"latest_commit_sha":null,"homepage":"","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/charkster.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-07-04T02:07:51.000Z","updated_at":"2022-04-08T00:14:07.000Z","dependencies_parsed_at":null,"dependency_job_id":"ef0f77e6-74bb-4b8a-b353-d20d8d78ff40","html_url":"https://github.com/charkster/SCARF","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/charkster/SCARF","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/charkster%2FSCARF","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/charkster%2FSCARF/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/charkster%2FSCARF/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/charkster%2FSCARF/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/charkster","download_url":"https://codeload.github.com/charkster/SCARF/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/charkster%2FSCARF/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":33588345,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-26T15:22:16.424Z","status":"online","status_checked_at":"2026-05-27T02:00:06.184Z","response_time":53,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","fpga-designs","raspberry-pi","scarf","spi-slave"],"created_at":"2024-11-14T04:17:26.278Z","updated_at":"2026-05-27T23:32:33.933Z","avatar_url":"https://github.com/charkster.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# SCARF\n![picture](https://github.com/charkster/SCARF/blob/master/docs/SCARF.png)\n\n**SCARF** - “**S**carf **C**onnects **A** **R**aspberry pi to **F**pga”\n\n**UART** and **SPI** data streams can be **difficult** to organize when a Host (Raspberry Pi or PC) communicates with a FPGA slave. **I2C** is very **structured** in how it allows a single Host to communicate with **multiple slaves**. I wanted to **merge** the **structured aspects** of I2C with the **high-throughput** and **full-duplex** capabilities of **UART** and **SPI**. This is what **SCARF is, I2C like communication over UART and SPI buses.** I provide the simple RTL and Python code to talk to it.\n\n**SCARF** really **shines** when the FPGA board has a **USB-UART** bridge chip, allowing the board to have **both power and communication on the same cable.** \n\nThe **first byte** sent to the FPGA contains the **Slave ID and Read-not-Write bit**. The most significant bit is the **RNW bit** and the lower 7bits are the **Slave ID**. The **Slave ID** allows different blocks on the FPGA to **ignore** bus traffic when their ID is not given. The provided RTL has the **Slave ID** defined as a parameter.\n\nThe next bytes are the **address data**. The provided RTL allows for a **parameterized** number of address bytes. A SDIO memory interface block might need many address bytes and a simple trigger block might just need a few bits from one byte of address data. The **number of address bytes is flexible**, but the RTL specified Slave ID and number of address bytes needs to be correctly transferred to the Python script.\n\nThe next bytes are either the **write data** or in the case of a **read, filler bytes** to keep the chip select active (**SPI**). When doing a read, if 5 bytes are wanted, 6 filler bytes need to be written to the FPGA. As **UART does not have a chip select**, I have a **SCARF** version where the **number of bytes** to read is used instead of filler bytes. The Python code fully takes care of these **finer details**, while remaining **easy to read and understand.**\n\nThe **maximum number** of read/write data bytes is **determined by the hardware SPI or UART master.** The provided RTL has **no limit.** If the FPGA board’s **USB-UART** bridge is used, the TX and RX buffers are **fixed in size** and must not be exceeded. If **SPI** is used, the **SPI** master’s transmit and receive byte **limits** also must be followed. The provided Python code has places for these limits to be specified.\n\nWhen read data returns to the Host, the **first byte sent by the FPGA will be the RNW bit and Slave ID.** This can be used similar to how a I2C master can quickly **query all slaves connected** to the bus. This byte can be safely discarded.\n\nThat’s it. My **Raspberry Pi** can reliably run a **SPI** clock of **12MHz**, and most FPGA on-board **USB-UART** bridges can run at **1M baud or faster.** \n\n**This repository only contains the SPI implementation of SCARF.** See this [document](https://github.com/charkster/mux_board_v1/blob/main/docs/intro_to_scarf.pdf) to learn about the **SPI** implementation.\n\nMy [tang_nano-uart_block_ram](https://github.com/charkster/tang_nano-uart_block_ram) repository has an excellent example of **UART SCARF**.\nThe [\"uart_byte_regmap_interface.sv\"](https://github.com/charkster/tang_nano-uart_block_ram/blob/main/fpga/src/uart_byte_regmap_interface.sv) file is the **SCARF RTL** block which converts the **UART** data stream into **reads and writes**. \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcharkster%2Fscarf","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcharkster%2Fscarf","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcharkster%2Fscarf/lists"}