{"id":16562793,"url":"https://github.com/charmve/accann","last_synced_at":"2026-03-06T09:04:59.629Z","repository":{"id":106309496,"uuid":"320448688","full_name":"Charmve/AccANN","owner":"Charmve","description":"🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*","archived":false,"fork":false,"pushed_at":"2023-02-25T02:45:44.000Z","size":404,"stargazers_count":15,"open_issues_count":3,"forks_count":1,"subscribers_count":2,"default_branch":"main","last_synced_at":"2024-04-15T09:05:26.474Z","etag":null,"topics":["accelerator","addernet","asic","charmve","cnn","deep-learning","fpga","fpga-hardware","ghostnet","gpu-acceleration","hardware","hardware-acceleration","neurips","paper","verilog"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Charmve.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2020-12-11T02:46:54.000Z","updated_at":"2024-03-15T00:22:32.000Z","dependencies_parsed_at":"2023-07-07T20:16:21.487Z","dependency_job_id":null,"html_url":"https://github.com/Charmve/AccANN","commit_stats":{"total_commits":28,"total_committers":1,"mean_commits":28.0,"dds":0.0,"last_synced_commit":"c6d2b31b331f3789157077f4f80e7dff647b3c75"},"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Charmve%2FAccANN","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Charmve%2FAccANN/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Charmve%2FAccANN/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Charmve%2FAccANN/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Charmve","download_url":"https://codeload.github.com/Charmve/AccANN/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":241975135,"owners_count":20051428,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["accelerator","addernet","asic","charmve","cnn","deep-learning","fpga","fpga-hardware","ghostnet","gpu-acceleration","hardware","hardware-acceleration","neurips","paper","verilog"],"created_at":"2024-10-11T20:37:10.716Z","updated_at":"2026-03-06T09:04:59.591Z","avatar_url":"https://github.com/Charmve.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# AccANN\nA compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for AdderNet.\n\n\u003cdiv align=center\u003e\u003cimg src=\"./img/figure/figure1.png\"\u003e\u003c/div\u003e\nFig 1. Visualization of features in AdderNets and CNNs. \u003csup\u003e[1]\u003c/sup\u003e\n\u003cbr\u003e\n\u003cdiv align=center\u003e\u003cimg src=\"./img/figure/figure2.png\"\u003e\u003c/div\u003e\nFig 2. Visualization of features in different neural networks on MNIST dataset. \u003csup\u003e[3]\u003c/sup\u003e\n\n## 🍮 Community\n- Github \u003ca href=\"https://github.com/Charmve/AccANN/discussions\" target=\"_blank\"\u003ediscussions 💬\u003c/a\u003e or \u003ca href=\"https://github.com/Charmve/AccANN/issues\" target=\"_blank\"\u003eissues 💭\u003c/a\u003e\n\n- QQ Group: 697948168 (password：AccANN)\n- Email: yidazhang#gmail.com \n\n## 🔗 Related Works\n\n[1] AdderNet: Do We Really Need Multiplications in Deep Learning? Hanting Chen, Yunhe Wang, Chunjing Xu, Boxin Shi, Chao Xu, Qi Tian, Chang Xu. CVPR, 2020. [📑[paper](https://arxiv.org/abs/1912.13200) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e[code](https://github.com/huawei-noah/AdderNet)]\n\n[2] AdderSR: Towards Energy Efficient Image Super-Resolution. Dehua Song, Yunhe Wang, Hanting Chen, Chang Xu, Chunjing Xu, Dacheng Tao. Arxiv, 2020. [📑[paper](https://arxiv.org/abs/2009.08891) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003ecode]\n\n[3] ShiftAddNet: A Hardware-Inspired Deep Network. Haoran You, Xiaohan Chen, Yongan Zhang, Chaojian Li, Sicheng Li, Zihao Liu, Zhangyang Wang, Yingyan Lin. NeurIPS, 2020. [📑[paper](https://arxiv.org/abs/2010.12785) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e[code](https://github.com/RICE-EIC/ShiftAddNet)]\n\n[4] Kernel Based Progressive Distillation for Adder Neural Networks. Yixing Xu, Chang Xu, Xinghao Chen, Wei Zhang, Chunjing XU, Yunhe Wang. NeurIPS, 2020. [📑[paper](https://arxiv.org/abs/2009.13044) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e[code]()]\n\n[5] GhostNet: More Features from Cheap Operations [📑[paper](https://arxiv.org/abs/1911.11907) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e[code](https://github.com/huawei-noah/ghostnet)]\n\n[6] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications [📑[paper](https://arxiv.org/abs/1704.04861) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e[code](https://github.com/Zehaos/MobileNet)]\n\n[7] VarGNet: Variable Group Convolutional Neural Network for Efficient Embedded Computing. Qian Zhang, Jianjun Li, Meng Yao. [📑[paper](https://arxiv.org/pdf/1907.05653v1.pdf) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e[code](https://github.com/zma-c-137/VarGFaceNet)]\n\n[8] And the bit goes down: Revisiting the quantization of neural networks (ICLR 2020). Pierre Stock, Armand Joulin, Remi Gribonval. [📑[paper](https://arxiv.org/pdf/1907.05686.pdf) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e[code](https://github.com/facebookresearch/kill-the-bits)]\n\n[9] DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs [📑[paper](https://docs.wixstatic.com/ugd/c50250_77e06b7f02b44eacb76c05e8fbe01e08.pdf) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e[code](https://github.com/IBM/AccDNN)]\n\n[10] AdderNet and its Minimalist Hardware Design for Energy-Efficient Artificial Intelligence. Yunhe Wang, Mingqiang Huang, Kai Han, et.al. [📑[paper](https://arxiv.org/pdf/2101.10015.pdf) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e code]\n\n[11] PipeCNN: An OpenCL-Based Open-Source FPGA Accelerator for Convolution Neural Networks. FPT 2017. Dong Wang, Ke Xu and Diankun Jiang. [📑[paper](https://arxiv.org/abs/1611.02450) | \u003cimg src=\"https://img.icons8.com/material-sharp/24/000000/github.png\" alt=\"Github\" width=\"22px\"/\u003e[code](https://github.com/doonny/PipeCNN)]\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcharmve%2Faccann","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fcharmve%2Faccann","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fcharmve%2Faccann/lists"}