{"id":26235859,"url":"https://github.com/cheeksthegeek/rtl-design","last_synced_at":"2026-02-25T14:07:31.101Z","repository":{"id":256836927,"uuid":"856554658","full_name":"CheeksTheGeek/rtl-design","owner":"CheeksTheGeek","description":"practicing creating meaningful real-world projects in Verilog/SystemVerilog","archived":false,"fork":false,"pushed_at":"2024-09-17T06:40:28.000Z","size":2070,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-13T03:18:12.563Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/CheeksTheGeek.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-09-12T19:20:26.000Z","updated_at":"2025-03-12T17:45:03.000Z","dependencies_parsed_at":"2024-09-13T10:23:21.294Z","dependency_job_id":null,"html_url":"https://github.com/CheeksTheGeek/rtl-design","commit_stats":null,"previous_names":["cheeksthegeek/rtl-design"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/CheeksTheGeek/rtl-design","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CheeksTheGeek%2Frtl-design","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CheeksTheGeek%2Frtl-design/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CheeksTheGeek%2Frtl-design/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CheeksTheGeek%2Frtl-design/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/CheeksTheGeek","download_url":"https://codeload.github.com/CheeksTheGeek/rtl-design/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/CheeksTheGeek%2Frtl-design/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":280857792,"owners_count":26403193,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-10-24T02:00:06.418Z","response_time":73,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-03-13T03:18:14.164Z","updated_at":"2025-10-24T19:42:40.371Z","avatar_url":"https://github.com/CheeksTheGeek.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003c!-- 2. **UART (Universal Asynchronous Receiver-Transmitter)** [UART Verilog(1) - EDA Playground](https://www.edaplayground.com/x/cj7A) [UART in VHDL and Verilog for an FPGA](https://nandland.com/uart-serial-port-module/) [GitHub - hell03end/verilog-uart: Simple 8-bit UART realization on Verilog HDL.](https://github.com/hell03end/verilog-uart) [GitHub - ben-marshall/uart: A simple implementation of a UART modem in Verilog.](https://github.com/ben-marshall/uart)\n   - A fundamental communication protocol used in embedded systems.\n3. **SPI (Serial Peripheral Interface)**\n   - Another common communication protocol for interfacing with sensors and peripherals.\n4. **I2C (Inter-Integrated Circuit)**\n   - A widely used communication protocol for connecting low-speed peripherals.\n5. **Ethernet MAC (Media Access Control)**\n   - Implementing the MAC layer of Ethernet for network communications.\n6. **VGA Controller**\n   - For displaying graphics on a VGA monitor.\n7. **DDR Memory Controller**\n   - Interface with DDR memory modules, crucial for high-speed data storage.\n8. **PCIe Interface**\n   - For high-speed data transfer between the FPGA and other hardware.\n9. **PWM (Pulse Width Modulation) Controller**\n   - Used in motor control and power regulation applications.\n10. **AES Encryption/Decryption Engine**\n   - Implementing hardware-based encryption for secure communications.\n11. **ADC/DAC Interface**\n    - Interfacing with Analog-to-Digital and Digital-to-Analog converters.\n12. **Digital Signal Processor (DSP)**\n    - For real-time signal processing applications.\n13. **JPEG Encoder/Decoder**\n    - Image compression and decompression in hardware.\n14. **FFT (Fast Fourier Transform) Processor**\n    - For frequency domain analysis and signal processing.\n15. **HDMI Transmitter/Receiver**\n    - For high-definition multimedia interface applications.\n16. **RISC-V Processor Core**\n    - Implementing a RISC-V CPU core, a popular open-source architecture.\n17. **CAN (Controller Area Network) Controller**\n    - Used in automotive and industrial control systems.\n18. **USB 2.0/3.0 Controller**\n    - For universal serial bus communication.\n19. **CPLD-based Logic Analyzer**\n    - For capturing and analyzing digital signals.\n20. **Smart Home Controller**\n    - For controlling various smart home devices.\n21. **Wireless Communication Module (e.g., Zigbee, Bluetooth)**\n    - For implementing wireless communication protocols. --\u003e\n\n# Verilogging : Logging my regular Verilog projects\n\nVerilogging is a small endeavour to practice creating meaningful real-world projects in Verilog, to make sure I don't lose the fun of it and to keep my skills sharp. \nI will be creating a few projects in Verilog and will be documenting them here. I will be using Icarus Verilog for simulation and GTKWave for waveform viewing.\n\n## Planned Projects\n\n- [x] Odd Even Transposition Sorting Network/Engine (Scalable) \n    This sorting engine aims to structurally parallelize a bubble sort-like algorithm to sort a list of numbers. The engine's external size parameters, like ARRAYLENGTH and DATAWIDTH are parameterized and the internal sizing gets calculated based on these parameters. The engine will be scalable and will be able to sort any list of numbers with any length and width less than 255.\n    The project's black-box idea was designed (as a deliverable for UWaterloo's ECE327: Digital Hardware Engineering Course) by William D. Bishop.\n- [x] Memory System Tester\n    Given a registered memory system of 256 Bytes, it tests every single bit of the system by reading and writing 1s and 0s in a pipelined fashion.\n    The project's black-box idea was designed (as a deliverable for UWaterloo's ECE327: Digital Hardware Engineering Course) by William D. Bishop.\n- [x] Pattern Detector\n- [x] Hamming Code Encoder and Decoder\n- [ ] UART Transmitter and Receiver\n    A UART Transmitter and Receiver module that can be used to send and receive data between different devices.    \n- [ ] SPI Master Transmitter and Receiver\n    A SPI Master Transmitter and Receiver module that can be used to send and receive data between different devices.\n- [ ] I2C Master Transmitter and Receiver\n    A I2C Master Transmitter and Receiver module that can be used to send and receive data between different devices.\n- [ ] Ethernet MAC\n    A Ethernet MAC module that can be used to send and receive data between different devices.\n- [ ] VGA Controller\n    A VGA Controller module that can be used to display graphics on a VGA monitor.\n- [ ] DDR Memory Controller\n    A DDR Memory Controller module that can be used to interface with DDR memory modules.\n- [ ] PCIe Interface\n    A PCIe Interface module that can be used to interface with PCIe devices.\n- [ ] PWM Controller\n    A PWM Controller module that can be used to generate PWM signals.\n- [ ] AES Encryption/Decryption Engine\n    A AES Encryption/Decryption Engine module that can be used to encrypt and decrypt data.\n- [ ] ADC/DAC Interface\n    A ADC/DAC Interface module that can be used to interface with ADC and DAC devices.\n- [ ] Digital Signal Processor (DSP)\n    A Digital Signal Processor (DSP) module that can be used to perform DSP operations.\n- [ ] JPEG Encoder/Decoder\n    A JPEG Encoder/Decoder module that can be used to encode and decode JPEG images.\n- [ ] FFT Processor\n    A FFT Processor module that can be used to perform FFT operations.\n- [ ] HDMI Transmitter/Receiver\n    A HDMI Transmitter/Receiver module that can be used to send and receive HDMI signals.\n- [ ] RISC-V Processor Core\n    A RISC-V Processor Core module that can be used to implement a RISC-V CPU core.\n- [ ] CAN Controller\n    A CAN Controller module that can be used to implement a CAN controller.\n- [ ] USB 2.0/3.0 Controller\n    A USB 2.0/3.0 Controller module that can be used to implement a USB controller.\n- [ ] CPLD-based Logic Analyzer\n    A CPLD-based Logic Analyzer module that can be used to capture and analyze digital signals.\n- [ ] Smart Home Controller\n    A Smart Home Controller module that can be used to control various smart home devices.\n- [ ] Wireless Communication Module (e.g., Zigbee, Bluetooth)\n    A Wireless Communication Module module that can be used to implement wireless communication protocols.\n\n## Larger Projects\n\n- [ ] RISC-V Processor Core\n    A RISC-V Processor Core module that can be used to implement a RISC-V CPU core.\n- [ ] A Neural Network\n    I haven't decided what kind of architecture I want to implement. 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