{"id":22880138,"url":"https://github.com/chili-chips-ba/opencologne","last_synced_at":"2026-01-26T21:52:06.660Z","repository":{"id":238976168,"uuid":"798146281","full_name":"chili-chips-ba/openCologne","owner":"chili-chips-ba","description":"Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =\u003e https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com ","archived":false,"fork":false,"pushed_at":"2025-10-16T06:57:48.000Z","size":310055,"stargazers_count":86,"open_issues_count":16,"forks_count":8,"subscribers_count":22,"default_branch":"main","last_synced_at":"2026-01-20T00:46:57.125Z","etag":null,"topics":["colognechip","design","digital","embedded","fpga","gatemate","hls","pcb","risc-v","rtl","soc","systemverilog"],"latest_commit_sha":null,"homepage":"https://nlnet.nl/project/openCologne","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/chili-chips-ba.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2024-05-09T07:23:51.000Z","updated_at":"2026-01-13T17:35:45.000Z","dependencies_parsed_at":null,"dependency_job_id":"d3cdafd9-9a4f-4b17-a317-214d2c9b093e","html_url":"https://github.com/chili-chips-ba/openCologne","commit_stats":null,"previous_names":["chili-chips-ba/opencologne"],"tags_count":3,"template":false,"template_full_name":null,"purl":"pkg:github/chili-chips-ba/openCologne","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chili-chips-ba%2FopenCologne","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chili-chips-ba%2FopenCologne/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chili-chips-ba%2FopenCologne/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chili-chips-ba%2FopenCologne/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/chili-chips-ba","download_url":"https://codeload.github.com/chili-chips-ba/openCologne/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chili-chips-ba%2FopenCologne/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28789194,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-26T21:49:50.245Z","status":"ssl_error","status_checked_at":"2026-01-26T21:48:29.455Z","response_time":59,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["colognechip","design","digital","embedded","fpga","gatemate","hls","pcb","risc-v","rtl","soc","systemverilog"],"created_at":"2024-12-13T17:16:25.410Z","updated_at":"2026-01-26T21:52:01.653Z","avatar_url":"https://github.com/chili-chips-ba.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"There is currently one and only one FPGA vendor in Europe -- CologneChip. Their GateMate device has a somewhat unique feature set for the 20K class, most notably the high-speed SerDes. It is also one of the rare families designed around 2-input [LUT trees and muxes](https://github.com/chili-chips-ba/openCologne/issues/28#issue-2442939220), vs. the mainstream microRAM-based LUTs with 4, 5 or 6 address inputs. \n\u003cp align=\"center\"\u003e\n   \u003cimg width=250 src=\"https://github.com/chili-chips-ba/openCologne/blob/main/0.doc/openCologne.logo.png\"\u003e\n\u003c/p\u003e\nGiven recent appearances of affordable boards, GateMate challenge at the moment is to get hold of, and grow roots in the open hardware dev community... which is also an opportunity. We are firmly set to help GateMate achieve this goal. \n\nHow? By pursuing a three-pronged approach:\n\n1) Design the third flavor of the popular open hardware ULX3S-\u003eULX4M sequel -\u003e\u003e\u003e The **ULX5M**! While LatticeSemi FPGA will on this new board be replaced with GateMate, it will otherwise come in the same popular Raspberry Pi Compute Module 4 (CM4) form-factor. That makes it plug-and-play compatible with a vast asssortment of baseboards, so opening the first and only EU FPGA to a commendable set of existing peripherals and apps.\n\n2) Create and validate a portfolio of **well-documented examples** that put GateMate resources to good use. Be it by tapping into SystemVerilog or VHDL RTL, HLS design methodologies, demonstrating pure hardware FSM implementations, or HW/SW co-design, utilizing SOC techniques, or possibly even reaching into Amaranth and LiteX build frameworks... the goal is to expand GateMate audience, faciliate silicon adoption, and ultimately have it gain a foothold in the market.\n\n3) Engage with [CologneChip](https://www.colognechip.com/programmable-logic/gatemate\"\u003eCologneChip) developers to resolve [issues](https://github.com/chili-chips-ba/openCologne/issues) identified in this course.\n\n\nThe practical execution of this strategy is organized into 3 game levels with 9 play milestones.\n\n## *Level I – Warm Up*\n\n**Play 1** - Form development team and get to know CologneChip GateMate silicon and dev tools, see our [0.doc](https://github.com/chili-chips-ba/openCologne/tree/main/0.doc) folder. Procure [Olimex](https://www.olimex.com/Products/FPGA/GateMate/GateMateA1-EVB/open-source-hardware) boards and familiarize with hardware platform. Light up onboard LEDs with our very special [blinky](https://github.com/chili-chips-ba/openCologne/tree/main/1.Blinky--Verilog-VHDL-Python.Amaranth/3.build). It contains _Verilog_, _VHDL_ and _Amaranth_ versions, as well as an example of how to use **CologneChip Internal Logic Analyzer (ILA)** for Olimex board. The **Makefile** and **CCF** in there are your essential _Getting Started Guide_, and golden reference to leverage from for your project.\n\n**Play 2** - Port to GateMate a selected subset of simpler examples from the [ULX3S-MISC](https://github.com/emard/ulx3s-misc/tree/master/examples) portfolio. The goal is to enable a few standard PMODs and peripherals, mostly GPIO-based, including PSRAM/HyperRAM.\n\n**Play 3** - To complement the set of peripherals that GateMate can be tested with, as well as design additional PMOD extensions for it.\n\n## *Level II - Bread and Butter*\n\n**Play 4** - Port to GateMate a couple of advanced ULX3S examples. Now without restrictions related to PCB development support, we are choosing these examples for their purely FPGA value. We may also modify them, write mutations and variants, looking to find a better fit for GateMate internal architecture, or letting creativity a free hand to play and experiment.\n\n**Play 5** - Adapt [TetriSaraj](https://github.com/chili-chips-ba/openXC7-TetriSaraj) HW/SW project to GateMate. This is a serious SOC. Its hardware includes a RISC-V microkontroller, Instruction, and Data RAM, Frame Buffer with Video Subsystem, and high-speed I/O for VGA. On the software side, this is a bare-metal, \"free-standing\" C that implements the logic of a Tetrisoid gate.\n\n**Play 6** - Design and manufacture the ULX5M board.\n\n## *Level III - Candy Cane*\n\n**Play 7** - Develop an advanced example for CologneChip SerDes and its high-speed PLL.\n\n**Play 8** - Stress-test the FPGA device and tools, such as to assess silicon Fmax and realistic utilization, injecting routing congestion and pushing the clock distribution network to its limits. \n\n**Play 9** - Port the barebones of [BetrustedSOC](https://github.com/betrusted-io/betrusted-soc) to GateMate, namely its VexRiscv CPU and UART.\n\nThis is a stepping stone for our next CologneChip project, perhaps using one of their yet to be released 40K or 80K devices. \n\nFor background, BetrustedSOC is currently hosted in a Spartan7 XC7S50 (50K LUT6 device), with 80% utilization (as of October 2022), implemented using proprietary Vivado 2019.2 toolchain, also enjoying a 5K LUT4 Lattice UP5 FPGA on the side for housekeeping tasks. The full BetrustedSOC would indeed be fun to eventually port to GateMate!\n\n## Project Completion Matrix\n\n- [x] Level I, Play 1 - **DONE, includes bonus examples**\n\u003e- [x] 1.Blinky--ILA-Test\n\u003e- [x] 1.Blinky--Verilog-VHDL-Python.Amaranth\n\n- [x] Level I, Play 2 - **DONE, with bonus examples**\n\u003e- [x] 2.Simple--1--PSRAM\n\u003e- [ ] 2.Simple--2--QSPI-Flash, WIP\n\u003e- [ ] 2.Simple--3--Ethernet, WIP\n\u003e- [x] 2.Simple--4--1Wire-Controller\n\u003e- [x] 2.Simple--5--UART-Test\n\u003e- [x] 2.Simple--6--PS2-Keyboard\n\u003e- [x] 2.Simple--7--Audio-4-bit-DAC\n\n- [ ] Level I, Play 3 - WIP\n\u003e - [ ] **PCB repo**: Design additional [extensions](https://github.com/intergalaktik/Extension_Boards_for_Olimex_GateMate), WIP\n\n---\n- [x] Level II, Play 4 - **DONE**, a very complex bonus example is in the works\n\u003e- [x] 4.Advanced--1--SPI-LCD\n\u003e- [x] 4.Advanced--2--LED64x64\n\u003e- [x] 4.Advanced--3--FM-Transmitter\n\u003e- [ ] 4.Advanced--4--Yamaha-OPL3-FM-Synth, WIP\n\n- [x] Level II, Play 5 - **DONE**, now also includes **bonus audio player** for any soundtrack, in addition to the original video-only game\n\u003e - [x] 5.TetriSaraj\n\n- [ ] Level II, Play 6\n\u003e- [ ] **PCB repo**: Design and manufacture the ULX5M board\n\n---\n- [ ] Level III, Play 7\n\u003e - [ ] 7.SerDes\n\n- [ ] Level III, Play 8\n\u003e - [ ] 8.StressTest, WIP\n\n- [ ] Level III, Play 9\n\u003e - [ ] 9.BetrustedSOC\n\n---\n- [ ] Bonus#1, Play 10, even more examples\n\u003e - [ ] 10.Bonus--1--Amaranth-7Segment, WIP\n\u003e - [ ] 10.Bonus--2--Amaranth-Rotary-Encoder, WIP\n\u003e - [ ] 10.Bonus--3--Amaranth-eduRISC5\n\u003e - [x] 10.Bonus--4--I2C-Master\n\u003e - [ ] 10.Bonus--5--eduSOC, WIP\n\u003e - [x] 10.Bonus--6--I2S-DAC\n\nWe fell in love with what we were doing and, as makers at heart, could not resist the temptation to keep designing for GateMate. Hence this additional output that was not originally planned for, nor commissioned by NLnet.\n\n---\nPlease click on the folder with individual examples for additional detail, documenation and specific instructions.\n\n\n## Bonus#2 (from CologneChip direct input/needs)\n- Comps with Gowin, Lattice and Xilinx design flows:\n    - overall execution speed\n    - ease of use\n    - straighforwardness (or not) of the work flow\n    - completeness of tool suite\n    - bugs and idiosyncrasies\n    - ideas for enhancement and automation of the development process\n\n- Comps with Gowin, Lattice and Xilinx silicon in the 20K LUT category\n    - Fmax\n    - utilization metrics\n    - practically achievable design sizes in LUTs and FFs, i.e. the overall efficiency of GateMate architecture\n\n- Misc.\n    - help prepare demos and marketing material for trade shows\n  \nWhile doing our best to fulfill these special requests that are outside the NLnet task list, we'd better plan for a follow up project for other CologneChip needs that are emerging through this work.\n\nFor example, we've already established that TetriSaraj (PicoSOC with PicoRV32) can on GateMate barely run at `31MHz` in its high Voltage setting `-om 3, -tm 3`, see this [issue](https://github.com/chili-chips-ba/openCologne/issues/35#issue-2529092332). On the other hand, the lowest speed-grade Artix7 (xc7a35tcpg236-1) had no problem with `100MHz+`. Moreover, this is not even an apples-to-apples comparison since, to make GateMate go over 25MHz (which is the absolute minimum for our VGA video sub-system), we had to strip the PicoSOC down to barebones, i.e. take out its features that were not critical for TetriSaraj. Without that, the original GateMate Fmax for the 100% identical RTL was on the order of `16MHz`.\n\nSimilarly, we found that GateMate [timing reporting](https://github.com/chili-chips-ba/openCologne/issues/35#issue-2529092332) was sub-standard, its [constraints-driven](https://github.com/chili-chips-ba/openCologne/issues/38) property questionable, [SystemVerilog](https://github.com/chili-chips-ba/openCologne/issues/3) support not built-in, simulation [models](https://github.com/chili-chips-ba/openCologne/issues/14) and [Verilator](https://github.com/chili-chips-ba/openCologne/issues/8) compatibility lacking. \n\nMost importantly, the `GateMate proprietary P_R tool has repeatedly proved to be erroneous and unreliable`, see issues https://github.com/chili-chips-ba/openCologne/issues/30 and https://github.com/chili-chips-ba/openCologne/issues/25. For the complete account, please review all discussions and issues we've raised, both open and closed.\n\n\u003e The good news is that, just as our project is uncovering issues, so is CologneChip addressing them... to slowly, step by step, turn GateMate tools and silicon into an FPGA platform that's actually useable in the real-life designs. \n\nWe are proud to have initiated GateMate enablement in opensource [Amaranth](https://github.com/amaranth-lang/amaranth) and [PipelineC](https://github.com/JulianKemmerer/PipelineC) dev frameworks. This project has also introduced GateMate to [Source Code Linting](https://github.com/chipsalliance/verible) for not only style, format, syntax and semantics, but also the [CDC](https://github.com/chili-chips-ba/openCologne/issues/29), a topic that is admittedly insufficiently covered by opensource chip design movement in general.\n\n## Beinvolved\nWe welcome everyone interested to contribute. Please reach out to fpga@chili-chips.com, or join our \u003ca href=\"https://discord.gg/F5UPDFFdsH\"\u003eGateMate Discord Channel\u003c/a\u003e. \n\n## Acknowledgements\nWe are grateful to:\n  - **NLnet Foundation's** sponsorship for this opportunity to put our hand and brains on GateMate.\n  - **[Intergalaktik doo](https://intergalaktik.eu)** for their unreserved sharing of the first-hand insights into open-source community vibe, participation on the project, and openess to our wish to play a part in the ULX* unabated evolution.\n\n\u003cp align=\"center\"\u003e\n    \u003cimg src=\"https://github.com/chili-chips-ba/openeye/assets/67533663/18e7db5c-8c52-406b-a58e-8860caa327c2\"\u003e\n    \u003cimg width=\"115\" alt=\"NGI-Entrust-Logo\" src=\"https://github.com/chili-chips-ba/openeye-CamSI/assets/67533663/013684f5-d530-42ab-807d-b4afd34c1522\"\u003e\n\u003c/p\u003e\n\n## Public Postings\n- [IO cards](https://www.linkedin.com/posts/goran-mahovlic_fpga-opensource-openhardware-activity-7272630456599138304-nB8K?utm_source=share\u0026utm_medium=member_desktop)\n- [TetriSaraj](https://www.linkedin.com/posts/chili-chips_tetrisaraj-gatemate-opensource-activity-7252167674741301249-gOgI?utm_source=share\u0026utm_medium=member_desktop)\n- [LED 64x64](https://www.linkedin.com/posts/ahmed-imamovic_etfpga-fpga-rtl-activity-7242253055411331073-E36f?utm_source=share\u0026utm_medium=member_desktop)\n- [LCD](https://www.linkedin.com/posts/chili-chips_gatemate-spi-lcd-activity-7233383297500733441-F4PM?utm_source=share\u0026utm_medium=member_desktop)\n\n\n#### End of Document\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchili-chips-ba%2Fopencologne","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchili-chips-ba%2Fopencologne","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchili-chips-ba%2Fopencologne/lists"}