{"id":13537309,"url":"https://github.com/chipsalliance/Cores-VeeR-EL2","last_synced_at":"2025-04-02T04:30:37.722Z","repository":{"id":43671575,"uuid":"232916517","full_name":"chipsalliance/Cores-VeeR-EL2","owner":"chipsalliance","description":"VeeR EL2 Core","archived":false,"fork":false,"pushed_at":"2024-10-31T16:38:51.000Z","size":283793,"stargazers_count":250,"open_issues_count":30,"forks_count":75,"subscribers_count":28,"default_branch":"main","last_synced_at":"2024-11-01T02:35:44.260Z","etag":null,"topics":["ahb-lite","asic-design","axi4","el2","fpga","fusesoc","open-source-hardware","processor","risc-v","riscv","riscv32","rtl","verilator","western-digital"],"latest_commit_sha":null,"homepage":"https://chipsalliance.github.io/Cores-VeeR-EL2/html/","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/chipsalliance.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-01-09T22:16:39.000Z","updated_at":"2024-10-24T11:13:30.000Z","dependencies_parsed_at":"2024-01-04T14:27:30.632Z","dependency_job_id":"13131f50-76fa-4527-a5d2-bfe810681a02","html_url":"https://github.com/chipsalliance/Cores-VeeR-EL2","commit_stats":null,"previous_names":["chipsalliance/cores-swerv-el2"],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FCores-VeeR-EL2","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FCores-VeeR-EL2/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FCores-VeeR-EL2/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FCores-VeeR-EL2/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/chipsalliance","download_url":"https://codeload.github.com/chipsalliance/Cores-VeeR-EL2/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246756827,"owners_count":20828774,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["ahb-lite","asic-design","axi4","el2","fpga","fusesoc","open-source-hardware","processor","risc-v","riscv","riscv32","rtl","verilator","western-digital"],"created_at":"2024-08-01T09:00:57.460Z","updated_at":"2025-04-02T04:30:37.716Z","avatar_url":"https://github.com/chipsalliance.png","language":"SystemVerilog","funding_links":[],"categories":["CPU cores","SystemVerilog","CPUs","Open Source Implementations"],"sub_categories":["Cores"],"readme":"\u003cpicture\u003e\n  \u003c!-- User prefers light mode: --\u003e\n  \u003csource srcset=\"docs/source/img/VeeR-logo-black-rgb.png\" media=\"(prefers-color-scheme: light)\"/\u003e\n\n  \u003c!-- User prefers dark mode: --\u003e\n  \u003csource srcset=\"/docs/source/img/VeeR-logo-white-rgb.png\"  media=\"(prefers-color-scheme: dark)\"/\u003e\n\n  \u003c!-- User has no color preference: --\u003e\n  \u003cimg src=\"/docs/source/img/VeeR-logo-black-rgb.png\"/\u003e\n\u003c/picture\u003e\n\n# VeeR EL2 RISC-V Core\n\nThis repository contains the VeeR EL2 RISC-V Core design RTL.\n\n## License\n\nBy contributing to this project, you agree that your contribution is governed by [Apache-2.0](LICENSE).  \nFiles under the [tools](tools/) directory may be available under a different license. Please review individual files for details.\n\n## Directory Structure\n\n    ├── configs                 # Configurations Dir\n    │   └── snapshots           # Where generated configuration files are created\n    ├── design                  # Design root dir\n    │   ├── dbg                 #   Debugger\n    │   ├── dec                 #   Decode, Registers and Exceptions\n    │   ├── dmi                 #   DMI block\n    │   ├── exu                 #   EXU (ALU/MUL/DIV)\n    │   ├── ifu                 #   Fetch \u0026 Branch Prediction\n    │   ├── include             \n    │   ├── lib\n    │   └── lsu                 #   Load/Store\n    ├── docs\n    ├── tools                   # Scripts/Makefiles\n    └── testbench               # (Very) simple testbench\n        ├── asm                 #   Example assembly files\n        ├── hex                 #   Canned demo hex files\n        └── tests               #   Example tests\n \n## Dependencies\n\n- Verilator **(4.106 or later)** must be installed on the system if running with Verilator\n- If adding/removing instructions, [`espresso`](https://github.com/chipsalliance/espresso/tree/master) must be installed (used by `tools/coredecode`). Remember to checkout on `3.x` branch.\n- RISCV tool chain (based on gcc version 8.3 or higher) must be\ninstalled so that it can be used to prepare RISCV binaries to run.\n\n## Quickstart guide\n\n1. Clone the repository, clone submodules with `git submodule update --init --recursive`\n1. Setup `RV_ROOT` to point to the path in your local filesystem\n1. Determine your configuration (optional)\n1. Run `make` with `tools/Makefile`\n\n## Release Notes for this version\n\nPlease see [release notes](release-notes.md) for changes and bug fixes in this version of VeeR.\n\n### Configurations\n\nVeeR can be configured by running the `$RV_ROOT/configs/veer.config` script:\n\n`% $RV_ROOT/configs/veer.config -h` for detailed help options\n\nFor example to build with a DCCM of size 64 Kb:  \n\n`% $RV_ROOT/configs/veer.config -dccm_size=64`  \n\nThis will update the **default** snapshot in `./snapshots/default/` with parameters for a 64K DCCM.  \n\nAdd `-snapshot=dccm64`, for example, if you wish to name your build snapshot `dccm64` and refer to it during the build.  \n\nThere are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via \nthe `-target=name` option to `veer.config`. **Note:** that the `typical_pd` target is what we base our published PPA numbers. It does not include an ICCM.\n\n**Building an FPGA speed optimized model:**\nUse ``-fpga_optimize=1`` option to ``veer.config`` to build a model that removes clock gating logic from flop model so that the FPGA builds can run at higher speeds. **This is now the default option for targets other than ``typical_pd``.**\n\n**Building a Power optimized model (ASIC flows):**\nUse ``-fpga_optimize=0`` option to ``veer.config`` to build a model that **enables** clock gating logic into the flop model so that the ASIC flows get a better power footprint. **This is now the default option for target``typical_pd``.**\n\nThis script derives the following consistent set of include files:\n\n    ./snapshots/default\n    ├── common_defines.vh                       # `defines for testbench or design\n    ├── defines.h                               # #defines for C/assembly headers\n    ├── el2_param.vh                            # Design parameters\n    ├── el2_pdef.vh                             # Parameter structure\n    ├── pd_defines.vh                           # `defines for physical design\n    ├── perl_configs.pl                         # Perl %configs hash for scripting\n    ├── pic_map_auto.h                          # PIC memory map based on configure size\n    └── whisper.json                            # JSON file for veer-iss\n    └── link.ld                                 # default linker control file\n\n### Building a model\n\nWhile in a work directory:\n\n1. Set the `RV_ROOT` environment variable to the root of the VeeR directory structure.\n\n   Example for bash shell: `export RV_ROOT=/path/to/veer` \n   Example for csh or its derivatives: `setenv RV_ROOT /path/to/veer`\n    \n1. Create your specific configuration\n\n   *(Skip if default is sufficient)*  \n   *(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)* \n\n   For example if `mybuild` is the name for the snapshot:\n\n   `$RV_ROOT/configs/veer.config [configuration options..] -snapshot=mybuild`  \n    \n   Snapshots are placed in the `./snapshots` directory\n\n1. Run a simple Hello World program (Verilator)\n\n   ```shell\n   make -f $RV_ROOT/tools/Makefile\n   ```\n\nThis command will build a Verilator model of VeeR EL2 with the AXI bus, and\nexecute a short sequence of instructions that writes out \"HELLO WORLD\"\nto the bus.\n\nThe simulation produces output on the screen like:\n\n```\nVerilatorTB: Start of sim\n\n-------------------------\nHello World from VeeR EL2\n-------------------------\nTEST_PASSED\n\nFinished : minstret = 437, mcycle = 922\nSee \"exec.log\" for execution trace with register updates..\n\n```\nThe simulation generates the following files:\n\n* `console.log` contains what the cpu writes to the console address of 0xd0580000.  \n* `exec.log` shows instruction trace with GPR updates.  \n* `trace_port.csv` contains a log of the trace port.  \n\nWhen `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by gtkwave or similar waveform viewers.\n  \nYou can re-execute the simulation using:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile verilator\n```\n\nThe simulation run/build command has following generic form:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile [\u003csimulator\u003e] [debug=1] [snapshot=mybuild] [target=\u003ctarget\u003e] [TEST=\u003ctest\u003e] [TEST_DIR=\u003cpath_to_test_dir\u003e]\n```\n\nwhere:\n\n``` \n\u003csimulator\u003e -  can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa\n               'riviera'- Aldec Riviera-PRO. if not provided, 'make' cleans work directory, builds verilator executable and runs a test.\ndebug=1     -  allows VCD generation for verilator and VCS and SHM waves for irun option.\nassert=1    -  enables assertions in simulation runs (with simulators other than Verilator)\n\u003ctarget\u003e    -  predefined CPU configurations 'default' ( by default), 'default_ahb', 'typical_pd', 'high_perf' \nTEST        -  allows to run a C (\u003ctest\u003e.c) or assembly (\u003ctest\u003e.s) test, hello_world is run by default \nTEST_DIR    -  alternative to test source directory testbench/asm or testbench/tests\n\u003csnapshot\u003e  -  run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument \n               for runs on custom configurations.\nCONF_PARAMS -  allows to provide -set options to veer.conf script to alter predefined EL2 targets parameters\n```\n\nExample:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile verilator TEST=cmark\n```\n\nwill build and simulate the `testbench/asm/cmark.c` program with Verilator.\n\nIf you want to compile a test only, you can run:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile program.hex TEST=\u003ctest\u003e [TEST_DIR=/path/to/dir]\n```\n\nThe Makefile uses the `snapshot/\u003ctarget\u003e/link.ld` file, generated by the `veer.conf` script by default to build the test executable.\nUser can provide test specific linker file in form `\u003ctest_name\u003e.ld` to build the test executable,\nin the same directory with the test source.\n\nUser also can create a test-specific Makefile in `\u003ctest_name\u003e.makefile`, containing building instructions\nhow to create the `program.hex` file used by simulation. The private Makefile should be in the same directory\nas the test source. See examples in the `testbench/asm` directory.\n\nAnother way to alter test building process is to use `\u003ctest_name\u003e.mki` file in test source directory. It may help to select multiple sources\nto compile and/or alter compilation swiches. See examples in the `testbench/tests/` directory\n \n*(the `program.hex` file is loaded to instruction and LSU bus memory slaves and optionally to DCCM/ICCM at the beginning of simulation)*.\n\nUser can build the `program.hex` file by any other means and then run simulation with the following command:\n\n```shell\nmake -f $RV_ROOT/tools/Makefile \u003csimulator\u003e\n```\n\nNote: You may need to delete the `program.hex` file from the work directory, when running a new test.\n\nThe  `$RV_ROOT/testbench/asm` directory contains the following tests ready to simulate:\n\n```\nhello_world       - default test program to run, prints Hello World message to screen and console.log\nhello_world_dccm  - the same as above, but takes the string from preloaded DCCM.\nhello_world_iccm  - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes\n                    it from there. Runs on EL2 with AXI4 buses only. \ncmark             - coremark benchmark running with code and data in external memories\ncmark_dccm        - the same as above, running data and stack from DCCM (faster)\ncmark_iccm        - the same as above with preloaded code to ICCM (slower, optimized for size to fit into default ICCM). \n\ndhry              - Run dhrystone. (Scale by 1757 to get DMIPS/MHZ)\n```\n\nThe `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISC-V SW tools are not installed.\n\n**Note**: The testbench has a simple synthesizable bridge that allows you to load the ICCM via load/store instructions. This is only supported for AXI4 builds.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2FCores-VeeR-EL2","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2FCores-VeeR-EL2","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2FCores-VeeR-EL2/lists"}