{"id":13537199,"url":"https://github.com/chipsalliance/aib-phy-hardware","last_synced_at":"2026-02-19T15:01:23.805Z","repository":{"id":41165212,"uuid":"235448474","full_name":"chipsalliance/aib-phy-hardware","owner":"chipsalliance","description":"Advanced Interface Bus (AIB) die-to-die hardware open source","archived":false,"fork":false,"pushed_at":"2024-09-23T03:09:01.000Z","size":41459,"stargazers_count":146,"open_issues_count":0,"forks_count":37,"subscribers_count":28,"default_branch":"master","last_synced_at":"2026-01-31T14:41:36.951Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/chipsalliance.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-01-21T21:49:19.000Z","updated_at":"2026-01-29T23:56:16.000Z","dependencies_parsed_at":"2025-02-15T15:54:31.476Z","dependency_job_id":"0b3cab13-a7ea-462a-9a7a-a14cd648a9ef","html_url":"https://github.com/chipsalliance/aib-phy-hardware","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/chipsalliance/aib-phy-hardware","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Faib-phy-hardware","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Faib-phy-hardware/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Faib-phy-hardware/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Faib-phy-hardware/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/chipsalliance","download_url":"https://codeload.github.com/chipsalliance/aib-phy-hardware/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Faib-phy-hardware/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29619098,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-19T13:04:20.082Z","status":"ssl_error","status_checked_at":"2026-02-19T13:03:33.775Z","response_time":117,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T09:00:56.203Z","updated_at":"2026-02-19T15:01:23.785Z","avatar_url":"https://github.com/chipsalliance.png","language":"Verilog","funding_links":[],"categories":["Connectivity","Verilog","AIB"],"sub_categories":[],"readme":"## Advanced Interface Bus (AIB) PHY\nThis repository contains the RTL and cell models for the AIB interface.  See the [AIB Spec](https://github.com/chipsalliance/AIB-specification) for the AIB Specification.\n\nSeptember 26, 2022\n\nAIB 1.0 Users (Spec rev 1.2) should go to Version 1.0 v1.0/rev2. \n\nAIB 2.0 Users (Spec rev 2.0.3) should go to Version 2.0 v2.0. \n\n\n## Version 1.0\n\n#### Version 1.0, Revision 1 (v1.0/rev1)\nThe rev1 open source AIB release is the same as the original moved from https://github.com/intel/aib-phy-hardware.\n\nThe rev1 directory structure is:                                    \n```aib_phy_hardware\n    ├── aib_lib\n    ├── docs\n    ├── how2use\n    ├── maib_rtl\n    ├── ndsimslv\n```\nSee README.txt under rev1 and subdirectories for detail.                  \nNew users should start with rev1 for quickest ramp up.                                   \n\n#### Version 1.0, Revision 2 (v1.0/rev2)\nRev2 has multi-die AIB instances and test benches.\n\nMain directory structure is below.  Read the README.txt files in the subdirectories for details.\n\n```aib_phy_hardware\n├── docs\n│   └── archive\n└── rev2              --  Multi-die AIBs design (for advanced user reference)\n    ├── dv            --  System Verilog DV to be released in the future.\n    │   ├── flist     --  File lists for multi-die AIB IPs.\n    │   ├── sims      --  Compilation directory. VCS is supported for now.\n    └── rtl           --  For the detail of the rtl release, see README.txt in this directory\n        ├── v1_master\n        ├── v1_slave\n        ├── v2_common\n        ├── v2_master\n        └── v2_slave\n```\n\n#### Version 1, FPGA Main Die AIB (MAIB)\nv1.0/rev2/rtl/v1_slave \n24 channel S10 MAIB Plus AUX (AUX only uses four pins)\nUse this for interop simulations with Stratix 10.\n\n## Version 2.0\n\nv2.0/rev1 is a behavioral model of AIB 2.0.\nv2.0/rev1.1 is RTL extracted from an actual AIB 2.0 design. Functionally rev1 and rev1.1 are intended to be equivalent. rev1 simulates a lot faster than rev1.1, so some people prefer to use rev1. For a tapeout, a user should run rev1.1 for final verification.\n\n#### Version 2.0 (v2.0/rev1)\nAIB 2.0 behavior RTL based on AIB spec 2.0.\n\n#### Version 2.0 (v2.0/rev1.1)\nMain directory structure is below.  Read the README.txt files in the subdirectories for details.\n\n```aib-phy-hardware\n├── docs\n│   └── archive\n├── v1.0\n│   ├── rev1             -- Previous rev1\n│   │   ├── aib_lib\n│   │   ├── how2use\n│   │   ├── maib_rtl\n│   │   ├── ndsimslv\n│   │   └── rtl\n│   └── rev2             -- Previous rev2 as above\n│       ├── constraints\n│       ├── dv\n│       └── rtl\n└── v2.0\n    ├── rev1           -- AIB model for AIB 2.0 Specification\n    │   ├── dv         -- System Verilog Verification Suite\n    │   └── rtl        -- Behavior RTL model\n    ├── rev1.1         -- MAIB 1.1\n        ├── dv\n        └── rtl        -- MAIB 1.1 model\n```\n#### FPGA Main Die AIB (MAIB)\nv2.0/rev1.1/rtl/maib_rev1.1\n24 channel Agilex with no AUX. The device_detect and power_on_reset signals go through a microbumped AUX channel on Agilex just like Stratix 10. \nThis model presents a MAIB MAC interface to FPGA soft IP, just like Quartus will provide.\nThe AUX connection of device_detect and power_on-reset is in the testbench.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Faib-phy-hardware","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2Faib-phy-hardware","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Faib-phy-hardware/lists"}