{"id":13416942,"url":"https://github.com/chipsalliance/chisel","last_synced_at":"2025-05-12T20:50:21.937Z","repository":{"id":31135837,"uuid":"34695562","full_name":"chipsalliance/chisel","owner":"chipsalliance","description":"Chisel: A Modern Hardware Design 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href=\"https://www.chisel-lang.org\"\u003e\n  \u003cimg src=\"https://raw.githubusercontent.com/chipsalliance/chisel/main/docs/src/images/chisel_logo.svg?sanitize=true\" height=\"60\"\u003e\n\u003c/a\u003e\n\u003ca href=\"https://www.chipsalliance.org\"\u003e\n  \u003cimg align=\"right\" src=\"https://raw.githubusercontent.com/chipsalliance/.github/main/profile/images/chips_alliance.svg?sanitize=true\" height=\"60\"\u003e\n\u003c/a\u003e\n\nThe **Constructing Hardware in a Scala Embedded Language** ([**Chisel**](https://www.chisel-lang.org)) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates **advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs**.\n\nChisel adds hardware construction primitives to the [Scala](https://www.scala-lang.org) programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog.\nThis generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the [Chisel Standard Library](https://www.chisel-lang.org/api/latest/#chisel3.util.package), raising the level of abstraction in design while retaining fine-grained control.\n\nFor more information on the benefits of Chisel see: [\"What benefits does Chisel offer over classic Hardware Description Languages?\"](https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages)\n\nChisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](https://github.com/chipsalliance/firrtl-spec),\na hardware compiler framework implemented by [LLVM CIRCT](https://github.com/llvm/circt).\n\nChisel is [permissively licensed](LICENSE) (Apache 2.0) under the guidance of [CHIPS Alliance](https://www.chipsalliance.org).\n\n- [What does Chisel code look like?](#what-does-chisel-code-look-like)\n  - [LED blink](#led-blink)\n  - [FIR Filter](#fir-filter)\n- [Getting Started](#getting-started)\n  - [Bootcamp Interactive Tutorial](#bootcamp-interactive-tutorial)\n  - [A Textbook on Chisel](#a-textbook-on-chisel)\n  - [Build Your Own Chisel Projects](#build-your-own-chisel-projects)\n  - [Guide For New Contributors](#guide-for-new-contributors)\n  - [Design Verification](#design-verification)\n- [Documentation](#documentation)\n  - [Useful Resources](#useful-resources)\n  - [Chisel Dev Meeting](#chisel-dev-meeting)\n  - [Data Types Overview](#data-types-overview)\n- [Contributor Documentation](#contributor-documentation)\n  - [Useful Resources for Contributors](#useful-resources-for-contributors)\n  - [Compiling and Testing Chisel](#compiling-and-testing-chisel)\n  - [Running Projects Against Local Chisel](#running-projects-against-local-chisel)\n  - [Chisel Architecture Overview](#chisel-architecture-overview)\n  - [Chisel Sub-Projects](#chisel-sub-projects)\n  - [Which version should I use?](#which-version-should-i-use)\n  - [Roadmap](#roadmap)\n\n---\n\n[![Join the chat at https://gitter.im/freechipsproject/chisel3](https://matrix.to/img/matrix-badge.svg)](https://gitter.im/freechipsproject/chisel3?utm_source=badge\u0026utm_medium=badge\u0026utm_campaign=pr-badge\u0026utm_content=badge)\n[![Scaladoc](https://www.javadoc.io/badge/org.chipsalliance/chisel_2.13.svg?color=blue\u0026label=Scaladoc)](https://javadoc.io/doc/org.chipsalliance/chisel_2.13/latest)\n![CI](https://github.com/chipsalliance/chisel/actions/workflows/test.yml/badge.svg)\n[![GitHub tag (latest SemVer)](https://img.shields.io/github/v/tag/chipsalliance/chisel.svg?include_prereleases\u0026sort=semver)](https://github.com/chipsalliance/chisel/releases/latest)\n[![Scala version support](https://index.scala-lang.org/chipsalliance/chisel/chisel/latest-by-scala-version.svg?platform=jvm)](https://index.scala-lang.org/chipsalliance/chisel/chisel)\n[![Scala version support (chisel3)](https://index.scala-lang.org/chipsalliance/chisel/chisel3/latest-by-scala-version.svg?platform=jvm)](https://index.scala-lang.org/chipsalliance/chisel/chisel3)\n[![Sonatype Snapshots](https://img.shields.io/nexus/s/org.chipsalliance/chisel_2.13?server=https%3A%2F%2Fs01.oss.sonatype.org)](https://s01.oss.sonatype.org/content/repositories/snapshots/org/chipsalliance/chisel_2.13)\n\n## What does Chisel code look like?\n\n### LED blink\n\n```scala\nimport chisel3._\nimport chisel3.util.Counter\nimport circt.stage.ChiselStage\n\nclass Blinky(freq: Int, startOn: Boolean = false) extends Module {\n  val io = IO(new Bundle {\n    val led0 = Output(Bool())\n  })\n  // Blink LED every second using Chisel built-in util.Counter\n  val led = RegInit(startOn.B)\n  val (_, counterWrap) = Counter(true.B, freq / 2)\n  when(counterWrap) {\n    led := ~led\n  }\n  io.led0 := led\n}\n\nobject Main extends App {\n  // These lines generate the Verilog output\n  println(\n    ChiselStage.emitSystemVerilog(\n      new Blinky(1000),\n      firtoolOpts = Array(\"-disable-all-randomization\", \"-strip-debug-info\")\n    )\n  )\n}\n```\n\nShould output the following Verilog:\n\u003c!--\nNote that you can regenerate the HTML below by using VSCode with extensions:\n* Markdown All in One: https://marketplace.visualstudio.com/items?itemName=yzhang.markdown-all-in-one\n* Verilog-HDL/SystemVerilog/Bluespec SystemVerilog: https://marketplace.visualstudio.com/items?itemName=mshr-h.VerilogHDL\n\nYou then generate the Verilog and place it in a syntax highlighted code block in this file, eg.\n```verilog\n...\n```\nYou can then run the command: \u003e Markdown All in One: Print current document to HTML\nThen you can open the generated HTML and copy-paste\n--\u003e\n\u003cdetails\u003e\n\u003csummary\u003eClick to expand!\u003c/summary\u003e\n\n\u003c/code\u003e\u003c/pre\u003e\n\u003cpre\u003e\u003ccode class=\"language-verilog\"\u003e\u003cspan class=\"hljs-comment\"\u003e// Generated by CIRCT firtool-1.37.0\u003c/span\u003e\n\u003cspan class=\"hljs-keyword\"\u003emodule\u003c/span\u003e Blinky(\n  \u003cspan class=\"hljs-keyword\"\u003einput\u003c/span\u003e  clock,\n         reset,\n  \u003cspan class=\"hljs-keyword\"\u003eoutput\u003c/span\u003e io_led0\n);\n\n  \u003cspan class=\"hljs-keyword\"\u003ereg\u003c/span\u003e       led;\n  \u003cspan class=\"hljs-keyword\"\u003ereg\u003c/span\u003e [\u003cspan class=\"hljs-number\"\u003e8\u003c/span\u003e:\u003cspan class=\"hljs-number\"\u003e0\u003c/span\u003e] counterWrap_c_value;\n  \u003cspan class=\"hljs-keyword\"\u003ealways\u003c/span\u003e @(\u003cspan class=\"hljs-keyword\"\u003eposedge\u003c/span\u003e clock) \u003cspan class=\"hljs-keyword\"\u003ebegin\u003c/span\u003e\n    \u003cspan class=\"hljs-keyword\"\u003eif\u003c/span\u003e (reset) \u003cspan class=\"hljs-keyword\"\u003ebegin\u003c/span\u003e\n      led \u0026lt;= \u003cspan class=\"hljs-number\"\u003e1\u0026#x27;h0\u003c/span\u003e;\n      counterWrap_c_value \u0026lt;= \u003cspan class=\"hljs-number\"\u003e9\u0026#x27;h0\u003c/span\u003e;\n    \u003cspan class=\"hljs-keyword\"\u003eend\u003c/span\u003e\n    \u003cspan class=\"hljs-keyword\"\u003eelse\u003c/span\u003e \u003cspan class=\"hljs-keyword\"\u003ebegin\u003c/span\u003e\n      \u003cspan class=\"hljs-keyword\"\u003eautomatic\u003c/span\u003e \u003cspan class=\"hljs-keyword\"\u003elogic\u003c/span\u003e counterWrap = counterWrap_c_value == \u003cspan class=\"hljs-number\"\u003e9\u0026#x27;h1F3\u003c/span\u003e;\n      led \u0026lt;= counterWrap ^ led;\n      \u003cspan class=\"hljs-keyword\"\u003eif\u003c/span\u003e (counterWrap)\n        counterWrap_c_value \u0026lt;= \u003cspan class=\"hljs-number\"\u003e9\u0026#x27;h0\u003c/span\u003e;\n      \u003cspan class=\"hljs-keyword\"\u003eelse\u003c/span\u003e\n        counterWrap_c_value \u0026lt;= counterWrap_c_value + \u003cspan class=\"hljs-number\"\u003e9\u0026#x27;h1\u003c/span\u003e;\n    \u003cspan class=\"hljs-keyword\"\u003eend\u003c/span\u003e\n  \u003cspan class=\"hljs-keyword\"\u003eend\u003c/span\u003e \u003cspan class=\"hljs-comment\"\u003e// always @(posedge)\u003c/span\u003e\n  \u003cspan class=\"hljs-keyword\"\u003eassign\u003c/span\u003e io_led0 = led;\n\u003cspan class=\"hljs-keyword\"\u003eendmodule\u003c/span\u003e\n\u003c/code\u003e\u003c/pre\u003e\n\n\u003c/details\u003e\n\n### FIR Filter\n\nConsider an FIR filter that implements a convolution operation, as depicted in this block diagram:\n\n\u003cimg src=\"https://raw.githubusercontent.com/chipsalliance/chisel/main/docs/src/images/fir_filter.svg?sanitize=true\" width=\"512\" /\u003e\n\nWhile Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such:\n\n```scala\n// 3-point moving sum implemented in the style of a FIR filter\nclass MovingSum3(bitWidth: Int) extends Module {\n  val io = IO(new Bundle {\n    val in = Input(UInt(bitWidth.W))\n    val out = Output(UInt(bitWidth.W))\n  })\n\n  val z1 = RegNext(io.in)\n  val z2 = RegNext(z1)\n\n  io.out := (io.in * 1.U) + (z1 * 1.U) + (z2 * 1.U)\n}\n```\n\nthe power of Chisel comes from the ability to create generators, such as an FIR filter that is defined by the list of coefficients:\n\n```scala\n// Generalized FIR filter parameterized by the convolution coefficients\nclass FirFilter(bitWidth: Int, coeffs: Seq[UInt]) extends Module {\n  val io = IO(new Bundle {\n    val in = Input(UInt(bitWidth.W))\n    val out = Output(UInt(bitWidth.W))\n  })\n  // Create the serial-in, parallel-out shift register\n  val zs = Reg(Vec(coeffs.length, UInt(bitWidth.W)))\n  zs(0) := io.in\n  for (i \u003c- 1 until coeffs.length) {\n    zs(i) := zs(i-1)\n  }\n\n  // Do the multiplies\n  val products = VecInit.tabulate(coeffs.length)(i =\u003e zs(i) * coeffs(i))\n\n  // Sum up the products\n  io.out := products.reduce(_ + _)\n}\n```\n\nand use and re-use them across designs:\n\n```scala\nval movingSum3Filter = Module(new FirFilter(8, Seq(1.U, 1.U, 1.U)))  // same 3-point moving sum filter as before\nval delayFilter = Module(new FirFilter(8, Seq(0.U, 1.U)))  // 1-cycle delay as a FIR filter\nval triangleFilter = Module(new FirFilter(8, Seq(1.U, 2.U, 3.U, 2.U, 1.U)))  // 5-point FIR filter with a triangle impulse response\n```\n\nThe above can be converted to Verilog using `ChiselStage`:\n\n```scala\nimport chisel3.stage.ChiselGeneratorAnnotation\nimport circt.stage.{ChiselStage, FirtoolOption}\n\n(new ChiselStage).execute(\n  Array(\"--target\", \"systemverilog\"),\n  Seq(ChiselGeneratorAnnotation(() =\u003e new FirFilter(8, Seq(1.U, 1.U, 1.U))),\n    FirtoolOption(\"--disable-all-randomization\"))\n)\n```\n\nAlternatively, you may generate some Verilog directly for inspection:\n\n```scala\nval verilogString = chisel3.getVerilogString(new FirFilter(8, Seq(0.U, 1.U)))\nprintln(verilogString)\n```\n\n## Getting Started\n\n### Bootcamp Interactive Tutorial\n\nThe [**online Chisel Bootcamp**](https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master) is the recommended way to get started with and learn Chisel.\n**No setup is required** (it runs in the browser), nor does it assume any prior knowledge of Scala.\n\nThe [**classic Chisel tutorial**](https://github.com/ucb-bar/chisel-tutorial) contains small exercises and runs on your computer.\n\n### A Textbook on Chisel\n\nIf you like a textbook to learn Chisel and also a bit of digital design in general, you may be interested in reading [**Digital Design with Chisel**](http://www.imm.dtu.dk/~masca/chisel-book.html). It is available in English, Chinese, Japanese, and Vietnamese.\n\n### Build Your Own Chisel Projects\n\nPlease see [the Installation page](https://www.chisel-lang.org/docs/installation) of the Chisel website for information about how to use Chisel locally.\n\nWhen you're ready to build your own circuits in Chisel, **we recommend starting from the [Chisel Template](https://github.com/chipsalliance/chisel-template) repository**, which provides a pre-configured project, example design, and testbench.\nFollow the [chisel-template README](https://github.com/chipsalliance/chisel-template) to get started.\n\nIf you insist on setting up your own project from scratch, your project needs to depend on both the chisel-plugin (Scalac plugin) and the chisel library.\nFor example, in SBT this could be expressed as:\n```scala\n// build.sbt\nscalaVersion := \"2.13.12\"\nval chiselVersion = \"6.0.0\"\naddCompilerPlugin(\"org.chipsalliance\" % \"chisel-plugin\" % chiselVersion cross CrossVersion.full)\nlibraryDependencies += \"org.chipsalliance\" %% \"chisel\" % chiselVersion\n```\n\nFor Chisel prior to v5.0.0, Chisel was published using a different artifact name:\n```scala\n// build.sbt\nscalaVersion := \"2.13.10\"\naddCompilerPlugin(\"edu.berkeley.cs\" % \"chisel3-plugin\" % \"3.6.0\" cross CrossVersion.full)\nlibraryDependencies += \"edu.berkeley.cs\" %% \"chisel3\" % \"3.6.0\"\n// We also recommend using chiseltest for writing unit tests\nlibraryDependencies += \"edu.berkeley.cs\" %% \"chiseltest\" % \"0.6.0\" % \"test\"\n```\n\n### Guide For New Contributors\n\nIf you are trying to make a contribution to this project, please read [CONTRIBUTING.md](CONTRIBUTING.md).\n\n### Design Verification\n\nThese simulation-based verification tools are available for Chisel:\n\n* [**svsim**](svsim) is the lightweight testing library for Chisel, included in this repository.\n* [**chiseltest (Chisel 6.0 and before)**](https://github.com/ucb-bar/chiseltest) is the batteries-included testing and formal verification library for Chisel-based RTL designs and a replacement for the former PeekPokeTester, providing the same base constructs but with a streamlined interface and concurrency support with `fork` and `join` with internal and Verilator integration for simulations.\n\n## Documentation\n\n### Useful Resources\n\n* [**Cheat Sheet**](https://github.com/freechipsproject/chisel-cheatsheet/releases/latest/download/chisel_cheatsheet.pdf), a 2-page reference of the base Chisel syntax and libraries\n* [**ScalaDoc (latest)**](https://www.chisel-lang.org/api/latest/index.html), a listing, description, and examples of the functionality exposed by Chisel, [older versions](https://www.chisel-lang.org/api/) are also available\n* [**Gitter**](https://gitter.im/freechipsproject/chisel3), where you can ask questions or discuss anything Chisel\n* [**Website**](https://www.chisel-lang.org) ([source](website))\n* [**Scastie (v6.0.0)**](https://scastie.scala-lang.org/CsDO7Q3TQHmBWJfKEB85Tw) - cannot generate Verilog (firtool does not work in Scastie)\n* [**Scastie (v3.6.0)**](https://scastie.scala-lang.org/1XICrlaZQs6ZvxpuKdFdDw) - generates Verilog with legacy Scala FIRRTL Compiler\n* [**asic-world**](http://www.asic-world.com/verilog/veritut.html) If you aren't familiar with verilog, this is a good tutorial.\n\nIf you are migrating from Chisel2, see [the migration guide](https://www.chisel-lang.org/chisel3/docs/appendix/chisel3-vs-chisel2.html).\n\n### Chisel Dev Meeting\n\nChisel/FIRRTL development meetings happen every Monday from 9:00-10:00 am PT.\n\nCall-in info and meeting notes are available [here](https://docs.google.com/document/d/1BLP2DYt59DqI-FgFCcjw8Ddl4K-WU0nHmQu0sZ_wAGo/).\n\n### Data Types Overview\n\nThese are the base data types for defining circuit components:\n\n![Image](https://raw.githubusercontent.com/chipsalliance/chisel/main/docs/src/images/type_hierarchy.svg?sanitize=true)\n\n## Contributor Documentation\n\nThis section describes how to get started contributing to Chisel itself, including how to test your version locally against other projects that pull in Chisel using [sbt's managed dependencies](https://www.scala-sbt.org/1.x/docs/Library-Dependencies.html).\n\n### Useful Resources for Contributors\n\nThe [Useful Resources](#useful-resources) for users are also helpful for contributors.\n\n* [**Chisel Breakdown Slides**](https://docs.google.com/presentation/d/1gMtABxBEDFbCFXN_-dPyvycNAyFROZKwk-HMcnxfTnU/edit?usp=sharing), an introductory talk about Chisel's internals\n\n### Compiling and Testing Chisel\n\nYou must first install required dependencies to build Chisel locally, please see [the installation instructions](https://www.chisel-lang.org/docs/installation).\n\nClone and build the Chisel library:\n\n```bash\ngit clone https://github.com/chipsalliance/chisel.git\ncd chisel\n./mill chisel[].compile\n```\n\nIn order to run the following unit tests, you will need several tools on your `PATH`, namely\n[verilator](https://www.veripool.org/verilator/),\n[yosys](https://yosyshq.net/yosys/),\nand [espresso](https://github.com/chipsalliance/espresso).\nCheck that each is installed on your `PATH` by running `which verilator` and so on.\n\nIf the compilation succeeded and the dependencies noted above are installed, you can then run the included unit tests by invoking:\n\n```bash\n./mill chisel[].test\n```\n\n### Running Projects Against Local Chisel\n\nTo use the development version of Chisel (`main` branch), you will need to build from source and publish locally.\nThe repository version can be found by running `./mill show unipublish.publishVersion`.\nAs of the time of writing it was: `7.0.0-M2+431-4798bea7-SNAPSHOT`\n\nTo publish your version of Chisel to the local Ivy repository, run:\n\n```bash\n./mill unipublish.publishLocal\n```\n\nThe compiled version gets placed in `~/.ivy2/local/org.chipsalliance/`.\nIf you need to un-publish your local copy of Chisel, remove the directory generated in `~/.ivy2/local/org.chipsalliance/`.\n\nIn order to have your projects use this version of Chisel, you should update the `libraryDependencies` setting in your project's build.sbt file to use the current version, for example:\n\n```scala\nval chiselVersion = \"7.0.0-M2+431-4798bea7-SNAPSHOT\"\naddCompilerPlugin(\"org.chipsalliance\" % \"chisel-plugin\" % chiselVersion cross CrossVersion.full)\nlibraryDependencies += \"org.chipsalliance\" %% \"chisel\" % chiselVersion\n```\n\n### Chisel Architecture Overview\n\nThe Chisel compiler consists of these main parts:\n\n* **The frontend**, `chisel3.*`, which is the publicly visible \"API\" of Chisel and what is used in Chisel RTL. These just add data to the...\n* **The Builder**, `chisel3.internal.Builder`, which maintains global state (like the currently open Module) and contains commands, generating...\n* **The intermediate data structures**, `chisel3.firrtl.*`, which are syntactically very similar to Firrtl. Once the entire circuit has been elaborated, the top-level object (a `Circuit`) is then passed to...\n* **The Firrtl emitter**, `chisel3.firrtl.Emitter`, which turns the intermediate data structures into a string that can be written out into a Firrtl file for further processing.\n\nAlso included is:\n\n* **The standard library** of circuit generators, `chisel3.util.*`. These contain commonly used interfaces and constructors (like `Decoupled`, which wraps a signal with a ready-valid pair) as well as fully parameterizable circuit generators (like arbiters and multiplexors).\n* **Chisel Stage**, `chisel3.stage.*`, which contains compilation and test functions that are invoked in the standard Verilog generation and simulation testing infrastructure. These can also be used as part of custom flows.\n\n### Chisel Sub-Projects\n\nChisel consists of several Scala projects; each is its own separate compilation unit:\n\n* [`core`](core) is the bulk of the source code of Chisel, depends on `firrtl`, `svsim`, and `macros`\n* [`firrtl`](firrtl) is the vestigial remains of the old Scala FIRRTL compiler, much if it will likely be absorbed into `core`\n* [`macros`](macros) is most of the macros used in Chisel, no internal dependencies\n* [`plugin`](plugin) is the compiler plugin, no internal dependencies\n* [`src/main`](src/main) is the \"main\" that brings it all together and includes a [`util`](src/main/scala/chisel3/util) library, which depends on `core`\n* [`svsim`](svsim) is a low-level library for compiling and controlling SystemVerilog simulations, currently targeting Verilator and VCS as backends\n\nCode that touches lots of APIs that are private to the `chisel3` package should belong in `core`, while code that is pure Chisel should belong in `src/main`.\n\n### Which version should I use?\n\nWe encourage Chisel users (as opposed to Chisel developers), to use the latest release version of Chisel.\nThis [chisel-template](https://github.com/chipsalliance/chisel-template) repository is kept up-to-date, depending on the most recent version of Chisel.\nThe recommended version is also captured near the top of this README, and in the [Github releases](https://github.com/chipsalliance/chisel/releases) section of this repo.\nIf you encounter an issue with a released version of Chisel, please file an issue on GitHub mentioning the Chisel version and provide a simple test case (if possible).\nTry to reproduce the issue with the associated latest minor release (to verify that the issue hasn't been addressed).\n\nFor more information on our versioning policy and what versions of the various Chisel ecosystem projects work together, see [Chisel Project Versioning](https://www.chisel-lang.org/chisel3/docs/appendix/versioning.html).\n\nIf you're developing a Chisel library (or `chisel3` itself), you'll probably want to work closer to the tip of the development trunk.\nBy default, the main branch of the chisel repository is configured to build and publish its version of the code as `\u003cversion\u003e+\u003cn\u003e-\u003ccommit hash\u003e-SNAPSHOT`.\nUpdated SNAPSHOTs are publised on every push to main.\nYou are encouraged to do your development against the latest SNAPSHOT, but note that neither API nor ABI compatibility is guaranteed so your code may break at any time.\n\n### Roadmap\n\nSee [Roadmap](ROADMAP.md).\n","funding_links":[],"categories":["Meta HDL and Transpilers","Scala","硬件_其他","Frameworks"],"sub_categories":["网络服务_其他"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Fchisel","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2Fchisel","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Fchisel/lists"}