{"id":18352695,"url":"https://github.com/chipsalliance/f4pga-sdf-timing","last_synced_at":"2025-04-06T11:33:01.684Z","repository":{"id":44875909,"uuid":"179588732","full_name":"chipsalliance/f4pga-sdf-timing","owner":"chipsalliance","description":"Python library for working Standard Delay Format (SDF) Timing Annotation files.","archived":false,"fork":false,"pushed_at":"2024-07-12T13:01:45.000Z","size":133,"stargazers_count":28,"open_issues_count":7,"forks_count":16,"subscribers_count":12,"default_branch":"master","last_synced_at":"2025-03-21T22:33:21.248Z","etag":null,"topics":["interconnect-delays","python-sdf-timing","sdf","symbiflow","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/chipsalliance.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-04-04T22:54:54.000Z","updated_at":"2024-08-28T08:55:36.000Z","dependencies_parsed_at":"2023-02-09T13:01:24.425Z","dependency_job_id":null,"html_url":"https://github.com/chipsalliance/f4pga-sdf-timing","commit_stats":null,"previous_names":["chipsalliance/python-sdf-timing"],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Ff4pga-sdf-timing","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Ff4pga-sdf-timing/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Ff4pga-sdf-timing/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Ff4pga-sdf-timing/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/chipsalliance","download_url":"https://codeload.github.com/chipsalliance/f4pga-sdf-timing/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247478152,"owners_count":20945258,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["interconnect-delays","python-sdf-timing","sdf","symbiflow","verilog"],"created_at":"2024-11-05T21:36:55.326Z","updated_at":"2025-04-06T11:33:01.267Z","avatar_url":"https://github.com/chipsalliance.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"# python-sdf-timing\n\nPython library for working Standard Delay Format (SDF) Timing Annotation files.\n\n\n# [Standard Delay Format](https://en.wikipedia.org/wiki/Standard_Delay_Format)\n\nFrom Wikipedia;\n\n\u003e Standard Delay Format (SDF) is an IEEE standard for the representation and\n\u003e interpretation of timing data for use at any stage of an electronic design\n\u003e process. It finds wide applicability in design flows, and forms an efficient\n\u003e bridge between\n\u003e [Dynamic timing verification](https://en.wikipedia.org/wiki/Dynamic_timing_verification) and\n\u003e [Static timing analysis](https://en.wikipedia.org/wiki/Dynamic_timing_verification).\n\u003e\n\u003e ...\n\u003e\n\u003e It is an ASCII format that is represented in a tool and language independent\n\u003e way and includes path delays, timing constraint values, interconnect delays\n\u003e and high level technology parameters.\n\u003e\n\u003e It has usually two sections: one for interconnect delays and the other for\n\u003e cell delays.\n\u003e\n\u003e SDF format can be used for back-annotation as well as forward-annotation.\n\n# Links\n\n * [python-sdf-timing GitHub Repository](https://github.com/chipsalliance/python-sdf-timing)\n * [SDF Parser written in C++](https://github.com/kmurray/libsdcparse) -\n * [Verilog To Routing](https://docs.verilogtorouting.org/en/latest/tutorials/timing_simulation/#post-imp-sdf) -\n   Verilog to Routing can generate an SDF file for doing post implementation timing simulation.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Ff4pga-sdf-timing","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2Ff4pga-sdf-timing","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Ff4pga-sdf-timing/lists"}