{"id":18352679,"url":"https://github.com/chipsalliance/f4pga-v2x","last_synced_at":"2025-04-06T11:33:00.808Z","repository":{"id":40297245,"uuid":"209179954","full_name":"chipsalliance/f4pga-v2x","owner":"chipsalliance","description":"Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.","archived":false,"fork":false,"pushed_at":"2024-08-14T07:49:51.000Z","size":754,"stargazers_count":10,"open_issues_count":48,"forks_count":13,"subscribers_count":12,"default_branch":"main","last_synced_at":"2025-04-04T22:45:51.840Z","etag":null,"topics":["f4pga","python","v2x","verilog","xml"],"latest_commit_sha":null,"homepage":"https://f4pga-v2x.readthedocs.io/en/latest/","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/chipsalliance.png","metadata":{"files":{"readme":"README.rst","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2019-09-18T00:13:51.000Z","updated_at":"2024-03-06T00:58:45.000Z","dependencies_parsed_at":"2022-08-09T16:44:51.753Z","dependency_job_id":null,"html_url":"https://github.com/chipsalliance/f4pga-v2x","commit_stats":null,"previous_names":["symbiflow/python-symbiflow-v2x"],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Ff4pga-v2x","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Ff4pga-v2x/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Ff4pga-v2x/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2Ff4pga-v2x/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/chipsalliance","download_url":"https://codeload.github.com/chipsalliance/f4pga-v2x/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247478152,"owners_count":20945258,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["f4pga","python","v2x","verilog","xml"],"created_at":"2024-11-05T21:36:49.557Z","updated_at":"2025-04-06T11:32:59.320Z","avatar_url":"https://github.com/chipsalliance.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"Verilog to Routing XML file generation from Verilog (`f4pga-v2x`)\n=================================================================\n\n\n.. image:: https://readthedocs.org/projects/f4pga-v2x/badge/?version=latest\n   :target: https://f4pga-v2x.readthedocs.io/en/latest/?badge=latest\n   :alt: Documentation Status\n\nv2x is a tool for converting specialized annotated Verilog models into XML needed for\n`Verilog to Routing flow \u003chttps://docs.verilogtorouting.org/en/latest/arch/reference/\u003e`_.\n\nDocumentation can be found at `https://f4pga-v2x.readthedocs.io/en/latest/ \u003chttps://f4pga-v2x.readthedocs.io/en/latest/\u003e`_.\n\nInstallation\n------------\n\nv2x can be installed from a local git repository using pip.\n\n.. code-block::\n\n   cd f4pga-v2x\n   pip install .\n\nAlternatively, it can be installed from GitHub directly.\n\n.. code-block::\n\n   pip install git+https://github.com/chipsalliance/f4pga-v2x.git#egg=f4pga-v2x\n\nUsage\n-----\n\nAfter installing v2x, you can run ``v2x`` to use it.\n\n.. code-block::\n\n   v2x -h\n   usage: __main__.py [-h] [--top TOP] [--outfile OUTFILE] [--includes INCLUDES]\n                      [--mode {pb_type,model}]\n                      input.v [input.v ...]\n\n   Verilog to XML\n\n   positional arguments:\n     input.v               One or more Verilog input files, that will be passed\n                           to Yosys internally. They should be enough to generate\n                           a flattened representation of the model, so that paths\n                           through the model can be determined.\n\n   optional arguments:\n     -h, --help            show this help message and exit\n     --top TOP             Top level module, will usually be automatically\n                           determined from the file name im.v\n     --outfile OUTFILE, -o OUTFILE\n                           Output filename, default 'output.xml'\n     --includes INCLUDES   Comma separate list of include directories.\n     --mode {pb_type,model}\n                           Output file type, possible values are: pb_type and\n                           model. Default value is pb_type\n\nFor example, to generate a pb_type xml file from adder.v, run\n\n.. code-block::\n\n   v2x -o adder.pb_type.xml adder.v\n\nOr, to generate a model xml file, run\n\n.. code-block::\n\n   v2x --mode model -o adder.model.xml adder.v\n\nv2x expects the module name to be the same as the file name. If it is different, make sure to specifiy it with the ``--top`` argument.\n\n.. code-block::\n\n   v2x --top BLOCK -o adder.pb_type.xml adder.v\n\nTests\n-----\n\nThe test cases are stored in tests/, and pytest can be used to run them.\n\n.. code-block::\n\n   rm -rf build  # run this step so that pytest uses the latest files for the tests\n   pytest -vv\n\nIf you are making changes to any python code, make sure that they follow the PEP8 style guide by running flake8.\n\n.. code-block::\n\n   flake8 tests\n   flake8 v2x\n\nDocumentation\n-------------\n\nWe use sphinx for our documentation and the files are stored in docs/. To host it locally (if you are planning to update it), you can use the Makefile inside.\n\nFirst, run ``make env`` to prepare a Conda environment that contains the necessary packages to build and host the documentation site. After that, simply run ``make livehtml`` which starts a local server running at port 8000 with the documentation site.\n\n.. code-block::\n\n   cd docs\n   make env\n   make livehtml\n\nTalks\n-----\n\n**VPR device models generation from Verilog with V2X - Karol Gugala - ORConf 2019**\n\n\n.. image:: https://img.youtube.com/vi/a31vH_tZLBM/0.jpg\n   :target: https://www.youtube.com/watch?v=a31vH_tZLBM\n   :alt: v2x orconf talk\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Ff4pga-v2x","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2Ff4pga-v2x","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Ff4pga-v2x/lists"}