{"id":13773654,"url":"https://github.com/chipsalliance/fpga-tool-perf","last_synced_at":"2025-04-06T11:33:03.159Z","repository":{"id":37101081,"uuid":"138338068","full_name":"chipsalliance/fpga-tool-perf","owner":"chipsalliance","description":"FPGA tool performance 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fpga-tool-perf\n\nAnalyze FPGA tool performance (MHz, resources, runtime, etc).\n\n## Setup\n\nfpga-tool-perf uses the Miniconda (conda) package manager to install and get all the required tools.\nCurrently, the following tools are available in conda:\n\n- vtr\n- nextpnr-xilinx\n- yosys (+ yosys-plugins)\n- prjxray\n\nPrior to setting up the conda environment, the F4PGA and QuickLogic data files need to be installed through the following commands:\n\n```bash\nmake install_f4pga\nmake install_quicklogic\n```\n\nThe install packages are extracted in `env/\u003ctoolchain\u003e/`.\n\nTo setup the conda environment, run the following commands:\n\n```bash\nTOOLCHAIN=f4pga make env\nTOOLCHAIN=quicklogic make env\nTOOLCHAIN=nextpnr make env\n```\n\nfpga-tool-perf can also run Vivado, which is not available in the conda environment and it needs to be installed by the user separately.\nThe user also needs to set the `VIVADO_SETTINGS` environmental variable, which points to the `settings64.sh` file to enable Vivado.\n\n## Running\n\nWith the conda environment correctly installed, run the following to activate the environment:\n\n```bash\nsource env.sh\n```\n\nOnce the environment settings have been sourced, you are ready to proceed with the tests, as described below.\n\n### Quick start example\n\n```bash\npython3 fpgaperf.py --toolchain vivado --project oneblink --board arty-a35t\n```\n\nor\n\n```bash\npython3 fpgaperf.py --toolchain vpr --project oneblink --board basys3\n```\n\nFor example, to compare a pure Vivado flow and Yosys -\u003e Vivado flow for an xc7z device, use the following:\n\n```bash\n# Yosys -\u003e Vivado\npython3 fpgaperf.py --toolchain yosys-vivado --project oneblink --board basys3\n# Pure Vivado\npython3 fpgaperf.py --toolchain vivado --project oneblink --board basys3\n```\n\nUse `--help` to see additional parameters for the `fpgaperf.py` script.\n\nSupported toolchains can be queried as follows:\n\n```bash\n$ python3 fpgaperf.py --list-toolchains\nnextpnr-ice40\nnextpnr-xilinx\nnextpnr-xilinx-fasm2bels\nvivado\nvpr\nvpr-fasm2bels\nyosys-vivado\n```\n\nYou can check if you have the toolchain environments correctly installed as follows:\n\n```bash\n$ python3 fpgaperf.py --check-env --toolchain vpr\nvpr\n  yosys: True\n  vpr: True\n  prjxray-config: True\n```\n\nSupported projects can be queried as follows:\n\n```bash\n$ python3 fpgaperf.py  --list-projects\nbaselitex\nblinky\nbram-n1\nbram-n2\nbram-n3\ndram-test-64x1d\nhamsternz-hdmi\nibex\nmurax\noneblink\npicorv32\npicosoc\npicosoc-simpleuart\npicosoc-spimemio\nvexriscv\nvexriscv-smp\n```\n\n### Exhaustive build\n\nUse `exhaust.py` to automatically test all projects, toolchain and boards supported:\n\n```bash\npython3 exhaust.py\n```\n\nIt's also possible to run a test against specific project(s), toolchain(s), and/or board(s):\n\n```bash\npython3 exhaust.py --project blinky oneblink --toolchain vpr\n```\n\nSee the `build` directory for output.\n\n## Project structure\n\nThis section describes the file and data structure used by this project to let you better understand its inner workings.\n\n- the `project` directory contains all the information relative to a specific test in respective YAML files. The data includes:\n  - srcs: all the source files needed to run the test\n  - top: top level module name of the design\n  - name: project name. Note: project names shouldn't contain underscores such that they are clearly separated from other fields when combined into folder names.\n  - data: all of the data/memory files needed to run the test\n  - clocks: all the input clocks of the design\n  - required\\_toolchains: all the toolchains that are required to correctly run to completion.\n  - vendors: all the vendors that are enabled for this project (e.g. xilinx, lattice). Each vendor requires a list of boards enabled for the test project.\n\n- the `src` directory contains all the source files needed to build the test project. It also contains the constraints files relative to the various boards supported.\n- the `other` directory contains two YAML configuration files, describing all the supported boards and vendors in this test suite.\n- the `toolchains` directory contains the Python scripts that enable a toolchain to be run within fpga-tool-perf.\n- the `infrastructure` directory contains Python scripts to control the fpga-tool-perf framework to run the tests\n\n## Development\n\n### Wrapper\n\n`wrapper.py` creates a simple Verilog interface against an arbitrary verilog module.\nThis allows testing arbitrary Verilog modules against a standard pin configuration. The rough idea is taken from Project X-Ray.\n\nRun `wrappers.sh` to regenerate all wrappers. Requires pyverilog.\n\n`wrapper.py` (iverilog based) has the following known limitations:\n * Bidrectional ports are not supported\n * Spaces inside numbers are not supported (ex: 8' h00 vs 8'h00)\n * Attributes (sometimes?) are not supported (ex: (* LOC=\"HERE\" *) )\n\nAs a result, sometimes the module definition is cropped out to make running the tool easier\n(ex: `src/picorv32/picosoc/spimemio.v` was cropped to `src/picosoc_spimemio_def.v`).\n\n### Inserting a New Project into fpga-tool-perf\n\nThese are the basic steps to inserting an existing project into fpga-tool-perf:\n\n#### *Step 1.*\n\nAdd a folder within `fpga-tool-perf/src` under the name of the project (make sure there are no underscores - '\\_' - in the name).\nFor example, for the project named counter:\n\n```bash\ncd ~/fpga-tool-perf/src\nmkdir counter\ncd counter\n```\n\nAdd the source (Verilog) and data/memory files to this directory.\n\nCreate a `constr` subdirectory, and within it, add the project's `.pcf` (for F4PGA) and `.xdc` (for Vivado) files under\nthe name of the board it uses.\n\n```bash\nmkdir constr\ntouch constr/basys3.pcf\ntouch constr/basys3.xdc\n```\n\nIf you don't have both the `.pcf` and `.xdc` files, you can look at the other projects for examples of how the `.xdc`\nand `.pcf` code correspond.\n\n#### *Step 2.*\n\nWithin the `project` directory, create a YAML file with the name of the project.\n\n```yaml\nsrcs:\n  - src/counter/counter.v\ntop: top\nname: counter\nclocks:\n  clk: 10.0\nvendors:\n  xilinx:\n    - arty-a35t\n    - arty-a100t\n    - basys3\nrequired_toolchains:\n  - vivado\n  - yosys-vivado\n  - vpr\n```\n\n#### *Step 3.*\n\nTest the newly added project with VPR and Vivado. For example:\n```\npython3 fpgaperf.py --project counter --toolchain vpr --board basys3\npython3 fpgaperf.py --project counter --toolchain vivado --board basys3\n```\n\nThere may be errors if your `.xdc` or `.pcf` files have the wrong syntax. Debug, modify, and run until it works, and you have successfully added a new project to fpga-tool-perf.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Ffpga-tool-perf","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2Ffpga-tool-perf","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Ffpga-tool-perf/lists"}