{"id":18352735,"url":"https://github.com/chipsalliance/omnixtendendpoint","last_synced_at":"2026-02-06T08:06:23.413Z","repository":{"id":77537632,"uuid":"577533681","full_name":"chipsalliance/OmnixtendEndpoint","owner":"chipsalliance","description":"Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.","archived":false,"fork":false,"pushed_at":"2026-01-29T00:07:38.000Z","size":281,"stargazers_count":19,"open_issues_count":0,"forks_count":5,"subscribers_count":4,"default_branch":"main","last_synced_at":"2026-01-31T14:41:40.678Z","etag":null,"topics":["asic","bluespec","coherence","fpga","omnixtend","tilelink"],"latest_commit_sha":null,"homepage":"","language":"Bluespec","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/chipsalliance.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2022-12-13T00:20:41.000Z","updated_at":"2026-01-29T00:07:43.000Z","dependencies_parsed_at":"2025-08-04T07:46:28.899Z","dependency_job_id":null,"html_url":"https://github.com/chipsalliance/OmnixtendEndpoint","commit_stats":null,"previous_names":["chipsalliance/omnixtendendpoint"],"tags_count":1,"template":false,"template_full_name":null,"purl":"pkg:github/chipsalliance/OmnixtendEndpoint","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FOmnixtendEndpoint","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FOmnixtendEndpoint/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FOmnixtendEndpoint/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FOmnixtendEndpoint/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/chipsalliance","download_url":"https://codeload.github.com/chipsalliance/OmnixtendEndpoint/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/chipsalliance%2FOmnixtendEndpoint/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29155107,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-06T07:18:23.844Z","status":"ssl_error","status_checked_at":"2026-02-06T07:13:32.659Z","response_time":59,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","bluespec","coherence","fpga","omnixtend","tilelink"],"created_at":"2024-11-05T21:37:06.755Z","updated_at":"2026-02-06T08:06:23.396Z","avatar_url":"https://github.com/chipsalliance.png","language":"Bluespec","funding_links":[],"categories":[],"sub_categories":[],"readme":"[![Issues][issues-shield]][issues-url]\n[![Apache 2.0 License][license-shield]][license-url]\n\n\u003cbr /\u003e\n\u003cdiv align=\"center\"\u003e\n\n  \u003ch3 align=\"center\"\u003eOmniXtend Endpoint\u003c/h3\u003e\n\n  \u003cp align=\"center\"\u003e\n    Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.\n    \u003cbr /\u003e\n    \u003cbr /\u003e\n    \u003ca href=\"https://github.com/chipsalliance/OmnixtendEndpoint/issues\"\u003eReport Bug\u003c/a\u003e\n    ·\n    \u003ca href=\"https://github.com/chipsalliance/OmnixtendEndpoint/issues\"\u003eRequest Feature\u003c/a\u003e\n  \u003c/p\u003e\n\u003c/div\u003e\n\n## About The Project\n\nOmniXtend is a protocol to transmit TileLink messages over Ethernet. The aim of the protocol is to create large fully coherent systems.\n\nThis repository contains a fully synthesizeable version of an OmniXtend 1.0.3 compatible memory endpoint. The endpoint supports TL-UL, TL-UH and TL-C type commands. In addition, the endpoint supports a proposed OmniXtend 1.1 standard with additional features and quality-of-life changes.\n\nFeatures:\n\n- AXI memory controllers (e.g., DDR 4/5, HBM).\n- Full Tilelink 1.8.0 feature set.\n- Variable length requests.\n- Multiple TileLink messages per Ethernet frame.\n- Written in [Bluespec][bluespec].\n- Compiles to Verilog, usable in most Hardware tool flows.\n\nView the [OmniXtend 1.0.3 Specification][oxspec] and the [TileLink 1.8.0 Specification][tlspec] for more information.\n\nThis repository contains additional tools for simulation:\n\n- `host_software/omnixtend-rs`: OmniXtend library written in Rust implementing a requester.\n- `host_software/omnixtend-tui`: TUI application to interact with OmniXtend endpoints.\n- `host_software/bitload`: Load data onto an OmniXtend endpoint over Ethernet.\n- `host_software/config`: Read status registers and configure the endpoint over PCIe (For [TaPaSCo][tapasco] designs only).\n\n\u003cp align=\"right\"\u003e(\u003ca href=\"#readme-top\"\u003eback to top\u003c/a\u003e)\u003c/p\u003e\n\n## Getting Started\n\nDepending on your use case you need to install some tools. This section details the different methods.\n\n### Prerequisites\n\n1. Bluespec Compiler: [bsc][bluespec]\n2. [BSVTools][bsvtools]: Provides the build system used by this project.\n3. (Optional: For simulation) Rust: [Rustup][rustup] recommended for installation.\n4. (Optional: For Xilinx FPGA/IP-XACT): [Vivado][vivado]\n\n### Setup\n\n1. Clone this repository with submodules\n\n```sh\ngit clone --recursive https://github.com/chipsalliance/OmnixtendEndpoint.git\n```\n\n2. Setup [BSVTools][bsvtools]\n\n```sh\ncd OmnixtendEndpoint\n${BSVTOOLS_PATH}/bsvAdd.py\n```\n\n### Running Simulations\n\nThere are three types of simulations provided. The first runs simple tests of the endpoint using Bluespec with a Rust stimulus.\n\nThe second method uses Rust to open a raw socket. This method allows interaction with the endpoint similarly to one in hardware over Ethernet.\n\nBoth methods require compiled simulation libraries\n\n```sh\ncd rust_sim\ncargo build --release\n```\n\n#### Internal Simulation\n\n```sh\nmake\n```\n\n### Socket Simulation\n\nThis method requires root access to create the raw sockets and the virtual Ethernet devices used to connect the endpoints/requesters.\n\n```sh\n./utils/run_socket.sh\n```\n\nBy default, creates five virtual Ethernet devices and attaches the endpoint to `veth0`. Attach your user software to `veth1-4`. The endpoint listens on the MAC address assigned to `veth0`, by default `04:00:00:00:00:00`.\n\nThe environment variable `linkcount` controls how many virtual Ethernet interfaces to create.\n\nAn example setup using `host_software/omnixtend-tui` is provided in `utils/run_tui_tmux.sh`. Before running this script, ensure that omnixtend-tui is compiled using:\n\n```sh\npushd host_software/omnixtend-tui\ncargo build --release\nsudo ../../utils/set_raw_cap.sh target/release/omnixtend-tui\npopd\n```\n\n#### Example Video\n\nhttps://user-images.githubusercontent.com/451732/208501480-c208613d-9103-4d5f-bde2-807261ebde84.mp4\n\n### Compiling to Verilog\n\n```sh\nmake SIM_TYPE=VERILOG compile_top\n```\n\nThis compiles the endpoint to Verilog files and places them in `build/verilog` and the top level is in `mkOmnixtendEndpoint.v`. This Verilog relies on primitives [distributed with the Bluespec compiler][bscsource].\n\n#### Integrated BRAM\n\nThe default configuration expects an AXI attached memory for storage. For simulation purposes a version with an integrated BRAM can be used instead:\n\n```sh\nmake SIM_TYPE=VERILOG BRAM_SIM=1 compile_top\n```\n\nThe BRAM is initialized using the Verilog function `$readmemh` from the file `memoryconfig.hex`.\n\n### Creating IP-XACT packet\n\nWith Vivado installed:\n\n```sh\nmake SIM_TYPE=VERILOG compile_top\n```\n\nThe IP-XACT contains all dependencies (e.g., [BSC primitives][bscsource]) and is located in `build/ip`.\n\n### Creating FPGA bitstream\n\nThe easiest way to create a bitstream for Xilinx based FPGA is using [TaPaSCo][tapasco]. `tapasco_job.json` is an example TaPaSCo job file for the Alveo U280 platform. TaPaSCo supports many additional platforms like the NetFPGA SUME or Bittware XUP-VVH.\n\n1. Install TaPaSCo according to the readme. Either by manually compiling or using their generated distribution packages. Source the TaPaSCo initialization script and ensure that `tapasco` is in your path.\n2. Import an IP-XACT core. This example uses an OmniXtend 1.0.3 configuration from the releases section.\n\n```sh\ntapasco import releases/OmnixtendEndpoint_RES_15_RESTO_21_ACKTO_12_OX11_0_MAC_0_CON_8_MAXFRAME_1500_MAXTLFRAME_1_BRAMSIM_0.zip as 412 --skipEvaluation -p AU280\n```\n\n3. Start bitstream generation using the job file.\n\n```sh\ntapasco --configFile tapasco_job.json\n```\n\nDepending on the target platform and available resources, the bitstream generation might take a while.\n\nThe generated bitstream contains one OmnixtendEndpoint connected to the default memory of the selected platform. PCIe exposes configuration and status registers. The tool `host_software/config` supports interacting with TaPaSCo generated bitstreams.\n\n## Configuration\n\nThe endpoint supports several configuration options:\n\n| Name                         | Use                                                                                                                                                                                      |\n| ---------------------------- | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |\n| `BRAM_SIM`                   | Use embedded BRAM instead of external AXI memory.                                                                                                                                        |\n| `OX_11_MODE`                 | Set to 1 to enable OmniXtend 1.1 features.                                                                                                                                               |\n| `RESEND_SIZE`                | Resend buffer size per connection. 2\\*\\*`RESEND_SIZE` flits.                                                                                                                             |\n| `RESEND_TIMEOUT_CYCLES_LOG2` | Force resend after 2\\*\\*`RESEND_TIMEOUT_CYCLES_LOG2` cycles without a valid packet.                                                                                                      |\n| `ACK_TIMEOUT_CYCLES_LOG2`    | Send ACK only packet after 2\\*\\*`ACK_TIMEOUT_CYCLES_LOG2` cycles.                                                                                                                        |\n| `OMNIXTEND_CONNECTIONS`      | Number of parallel connections.                                                                                                                                                          |\n| `MAXIMUM_PACKET_SIZE`        | Maximum number of bytes in Ethernet packet. Set to 1500 for default.                                                                                                                     |\n| `MAXIMUM_TL_PER_FRAME`       | Maximum number of TileLink messages per Ethernet packet generated by this IP. Between 1 and 64.                                                                                          |\n| `MAC_ADDR`                   | Default MAC address. Set as hexadecimal without any prefix, e.g., `040000000000`.                                                                                                        |\n| `SYNTH_MODULES`              | Split out Bluespec modules into separate Verilog modules. Default creates a single Verilog file. Useful for some downstream tools that have a hard time processing the flattened design. |\n\n## Contributing\n\nContributions are what make the open source community such an amazing place to be, learn, inspire, and create. We **greatly appreciated** any contributions you make.\n\n1. Fork the Project\n2. Create your Feature Branch (`git checkout -b feature/AmazingFeature`)\n3. Commit your Changes (`git commit -m 'Add some AmazingFeature'`)\n4. Push to the Branch (`git push origin feature/AmazingFeature`)\n5. Open a Pull Request\n\n\u003cp align=\"right\"\u003e(\u003ca href=\"#readme-top\"\u003eback to top\u003c/a\u003e)\u003c/p\u003e\n\n## License\n\nDistributed under the Apache 2.0 license. See `LICENSE` for more information.\n\n\u003cp align=\"right\"\u003e(\u003ca href=\"#readme-top\"\u003eback to top\u003c/a\u003e)\u003c/p\u003e\n\nThis Readme is based on [Best-README-Template](https://github.com/othneildrew/Best-README-Template).\n\n[bscsource]: https://github.com/B-Lang-org/bsc/tree/main/src/Verilog\n[vivado]: https://www.xilinx.com/products/design-tools/vivado.html\n[bsvtools]: https://github.com/esa-tu-darmstadt/BSVTools\n[rustup]: https://rustup.rs/\n[tapasco]: https://github.com/esa-tu-darmstadt/tapasco\n[bluespec]: https://github.com/B-Lang-org/bsc\n[oxspec]: https://github.com/chipsalliance/omnixtend/blob/master/OmniXtend-1.0.3/spec/OmniXtend-1.0.3.pdf\n[tlspec]: https://github.com/chipsalliance/omnixtend/blob/master/OmniXtend-1.0.3/spec/TileLink-1.8.0.pdf\n[issues-shield]: https://img.shields.io/github/issues/chipsalliance/OmnixtendEndpoint.svg?style=for-the-badge\n[issues-url]: https://github.com/chipsalliance/OmnixtendEndpoint/issues\n[license-shield]: https://img.shields.io/github/license/chipsalliance/OmnixtendEndpoint.svg?style=for-the-badge\n[license-url]: https://github.com/chipsalliance/OmnixtendEndpoint/blob/master/LICENSE\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Fomnixtendendpoint","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fchipsalliance%2Fomnixtendendpoint","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fchipsalliance%2Fomnixtendendpoint/lists"}